V58C2128(804/404/164)SC
HIGH PERFORMANCE 128 Mbit DDR SDRAM
4 BANKS X 4Mbit X 8 (804)
4 BANKS X 2Mbit X 16 (164)
4 BANKS X 8Mbit X 4 (404)
4
DDR500
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
7.5 ns
6ns
4ns
250 MHz
5
DDR400
7.5 ns
6ns
5ns
200 MHz
6
DDR333
7.5 ns
6 ns
6 ns
166 MHz
Features
■
High speed data transfer rates with system frequency
up to 200 MHz
■
Data Mask for Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 2.5, 3
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 4096 cycles/64 ms
■
Available in 66-pin 400 mil TSOP or 60 Ball FBGA
■
SSTL-2 Compatible I/Os
■
Double Data Rate (DDR)
■
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
Differential clock inputs CK and CK
■
Power Supply 2.5V ± 0.2V for DDR333
■
Power Supply 2.5V ± 0.1V for DDR400 & DDR500
■
tRAS lockout supported
■
Concurrent auto precharge option is supported
*Note:
(-4) Supports 3-4-4 timing
(-5) Supports 3-3-3 timing
(-6) Supports 2.5-3-3 timing
Description
The V58C2128(804/404/164)SC is a four bank DDR
DRAM organized as 4 banks x 4Mbit x 8 (804), 4 banks x
2Mbit x 16 (164), or 4 banks x 8Mbit x 4 (404). The
V58C2128(804/404/164)SC achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 FBGA
•
CK Cycle Time (ns)
-4
•
Power
-6
•
-5
•
Std.
•
L
•
Temperature
Mark
Blank
V58C2128(804/404/164)SC Rev.1.2 December 2007
1
ProMOS TECHNOLOGIES
V58C2128(804/404/164)SC
Block Diagram
Column Addresses
32M x 4
Row Addresses
A0 - A11, BA0, BA1
A0 - A9, A11, AP, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
4096 x 1024
x8
4096 x 1024
x8
Column decoder
Sense amplifier & I(O) bus
4096 x 1024
x8
Column decoder
Sense amplifier & I(O) bus
4096 x 1024
x8
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
3
CKE
RAS
CAS
WE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DM
CK
CK
CS
DQS
V58C2128(804/404/164)SC Rev. 1.2 December 2007
5
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