73M1903C
Modem Analog Front End
DATA SHEET
SEPTEMBER 2006
DESCRIPTION
The TERIDIAN 73M1903C Analog Front End
(AFE) IC includes fully differential hybrid driver
outputs, which connect to the telephone line
interface through a transformer-based DAA. The
receive pins are also fully differential for
maximum flexibility and performance. This
arrangement allows for the design of a high
performance hybrid circuit to improve signal to
noise performance under low receive level
conditions, and compatibility with any standard
transformer intended for PSTN communications
applications.
The device incorporates a programmable sample
rate circuit to support soft modem and DSP
based implementations of all speeds up to V.92
(56Kbps). The sampling rates supported are from
7.2KHz to 16.0KHz by programming the pre-
scaler NCO and the PLL NCO.
The TERIDIAN 73M1903C device incorporates a
digital host interface that is compatible with the
serial ports found on most commercially available
DSPs and processors and exchanges both
payload and control information with the host.
This interface can be configured as a single
master/slave mode or as a daisy chain mode that
allows the user to connect up to eight 73M1903C
devices to a single host for multi Analog Front
End applications, such as, central server
modems.
Costs saving features of the device include an
input reference frequency circuit, which accepts a
range of crystals from 4.9-27MHz. It also accepts
external reference clock values between 1MHz-
40MHz generated by the host processor. In most
applications, this eliminates the need for a
dedicated crystal oscillator and reduces the bill of
material (BOM).
The 73M1903C also supports two analog loop
back and one digital loop back test modes.
Features
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Two pairs of software selectable transmit
differential outputs for worldwide impedance
driver implementations.
Up to 56Kbps (V.92) performance
Programmable sample rates (7.2-16.0KHz)
Reference clock range of 1-40MHz
Crystal frequency range of 4.9-27MHz
Master or slave mode operation and daisy
chain configurable synchronous serial Host
interface
Low power modes
Fully differential receiver and transmitter
Drivers for transformer interface
3.0V – 3.6V operation
5V tolerant I/O
Industrial temperature range (-40 to +85°C)
JATE compliant transmit spectrum
Package options: 32 pin QFN
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Applications
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Central site server modems
Set Top Boxes
Personal Video Recorders (PVR)
Multifunction Peripherals (MFP)
Fax Machines
Internet Appliances
Game Consoles
Point of Sale Terminals
Automatic Teller Machines
Speaker Phones
Digital Answering Machines
RF Modems
VBG
(HYBRID)
TXAP1
TXAN1
TXAP2
TXAN2
RXAP
RXAN
Transmit
Drivers/
Filters
Receiver
MUX/
Filters
Analog
Sigma
Delta
Ref.
SCLK
Control
Registers
SDIN
Serial
Port
SDOUT
FS
Control
Logic
FSBD
DAC
GPIO
HOOK
DAA
controls
Clock
Crystal
Page: 1 of 45
©
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
73M1903C
Modem Analog Front End
DATA SHEET
Table of Contents
DESCRIPTION.............................................................................................................................................. 1
Features ........................................................................................................................................................ 1
Applications................................................................................................................................................... 1
CONTROL REGISTER MAP ........................................................................................................................ 9
ANALOG I/O ............................................................................................................................................... 11
CLOCK GENERATION ............................................................................................................................... 13
MODEM RECEIVER ................................................................................................................................... 19
MODEM TRANSMITTER............................................................................................................................ 23
TEST MODES............................................................................................................................................. 27
POWER SAVING MODES.......................................................................................................................... 27
ELECTRICAL SPECIFICATIONS............................................................................................................... 28
ABSOLUTE MAXIMUM RATINGS.......................................................................................................... 28
RECOMMENDED OPERATING CONDITIONS...................................................................................... 28
DIGITAL SPECIFICATIONS ....................................................................................................................... 29
DC CHARACTERISTICS ........................................................................................................................ 29
AC TIMING .............................................................................................................................................. 30
ANALOG SPECIFICATIONS ...................................................................................................................... 31
DC SPECIFICATIONS ............................................................................................................................ 31
AC SPECIFICATIONS............................................................................................................................. 31
PERFORMANCE..................................................................................................................................... 32
PACKAGE OPTIONS.................................................................................................................................. 34
MECHANICAL DRAWINGS........................................................................................................................ 35
APPENDIX A............................................................................................................................................... 36
73M1903C DAA Resistor Calculation Guide........................................................................................... 36
APPENDIX B............................................................................................................................................... 39
Crystal Oscillator ..................................................................................................................................... 39
PLL .......................................................................................................................................................... 40
Examples of NCO settings ...................................................................................................................... 41
ORDERING INFORMATION....................................................................................................................... 45
Page: 2 of 45
©
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
73M1903C
Modem Analog Front End
DATA SHEET
List of Figures
Figure 1: 73M1903C Host connection in master and slave mode ................................................................ 6
Figure 2: 73M1903C Daisy chaining for master/slave mode and slave modes............................................ 6
Figure 3: SCLK,
FS,
and FSBD .................................................................................................................... 8
Figure 4: Control frame position vs. SPOS ................................................................................................... 9
Figure 5: Serial Port Timing Diagrams........................................................................................................ 10
Figure 6: Analog block diagram .................................................................................................................. 12
Figure 7: Clock Generation ......................................................................................................................... 19
Figure 8: Overall Receiver Frequency Response ....................................................................................... 20
Figure 9: Rx Path Passband Response...................................................................................................... 21
Figure 10: RXD Spectrum of 1kHz tone...................................................................................................... 22
Figure 11: RXD Spectrum of 0.5kHz, 1kHz, 2kHz, 3kHz and 3.5kHz tones of Equal Amplitudes ............. 22
Figure 12: Frequency Response of TX Path for DC to 4kHz in band Signal.............................................. 23
Figure 13: Serial Port Data Timing.............................................................................................................. 30
Page: 3 of 45
©
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
73M1903C
Modem Analog Front End
DATA SHEET
SIGNAL DESCRIPTION
The TERIDIAN 73M1903C modem AFE IC is available in a 32 pin QFN package with same pin out. The
following table describes the function of each pin. There are two pairs of power supply pins, VPA
(analog) and VPD (digital). They should be separately decoupled from the supply source in order to
isolate digital noise from the analog circuits internal to the chip. Failure to adequately isolate and
decouple these supplies will compromise device performance.
PIN NAME
VND
VNA
VPD
VPA
VPPLL
VNPLL
TYPE
GND
GND
PWR
PWR
PWR
PWR
PIN #
1, 22
16
2, 25
9
20
17
DESCRIPTION
Negative Digital Ground
Negative Analog Ground
Positive Digital Supply
Positive Analog Supply
Positive PLL Supply, shared with VPD
Negative PLL Ground
Master reset. When this pin is a logic 0 all registers are reset to their
default states; Weak-pulled high-default. A low pulse longer than 100ns
is needed to reset the device. The device will be ready within 100us after
this pin goes to logic 1 state.
Crystal oscillator input. When providing an external clock source, drive
OSCIN.
Crystal oscillator circuit output pin.
Software definable digital input/output pins.
Receive analog negative input.
Receive analog positive input.
Transmit analog negative output 1
Transmit analog negative output 2
Transmit analog positive output 1
Transmit analog positive output 2
Serial interface clock. With master mode and SCLK continuous selected,
Freq = 256*Fs ( =2.4576MHz for Fs=9.6kHz). For slave mode, this pin
must be pulled down by a resistor (<4.7kΩ).
Serial data output (or input to the host).
Serial data input (or output from the host)
Frame synchronization. (Active Low)
Reserved
Controls the SCLK behavior after FS. Open, weak-pulled high = SCLK
Continuous; tied low = 32 clocks per R/W cycle.
Delayed frame sync to support daisy chain mode with additional
73M1903C devices
RST
I
26
OSCIN
OSCOUT
GPIO(0-7)
RXAN
RXAP
TXAN1
TXAN2
TXAP1
TXAP2
SCLK
SDOUT
SDIN
FS
TEST
SckMode
FSBD
I
O
I/O
I
I
O
O
O
O
I/O
O
I
O
I
I
O
19
18
3, 4, 5, 6, 23 24,
30, 31
14
15
10
11
12
13
8
32
29
7
27
28
21
Table 1: -32 QFN Pin Description
Page: 4 of 45
©
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
73M1903C
Modem Analog Front End
DATA SHEET
SERIAL INTERFACE
The serial data port is a bi-directional port that can be supported by most DSPs. The 73M1903C can be
configured either as a master or a slave of the serial interface. When the 73M1903C is configured as a
master device, it generates a serial bit clock, Sclk, from a system clock, Sysclk, which is normally an
output from an on-chip PLL that can be programmed by the user. In master mode, the serial bit clock is
always derived by dividing the system clock by 18. The sclk rate, Fsclk, is related to the frame
synchronization rate, Fs, by the relationship Fsclk = 256 x Fs or Fs = Fsclk / 256 = Fsys / 18 / 256 = Fsys
/ 4608, where Fsys is the frequency of Sysclk. Fs is also the rate at which both transmit and receive data
bytes are sent (received) to (by) the Host. Throughout this document two pairs of sample rate, Fs, and
crystal frequency, Fxtal, will be often cited to facilitate discussions. They are:
1. Fxtal
1
= 27MHz, Fs
1
= 7.2kHz
2. Fxtal
2
= 18.432MHz, Fs
2
= 8kHz.
3. Fxtal
3
= 24.576MHz, Fs
3
= 9.6kHz
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal
1
= 27.000MHz, then sclk=1.500MHz and Fs=sclk/256 = 5.859375kHz.
2. If Fxtal
2
= 18.432MHz, then sclk=1.024MHz and Fs=sclk/256 = 4.00kHz.
3. If Fxtal
3
= 24.576MHz, then sclk=1.3653MHz and Fs=sclk/256 = 5.33kHz.
When 73M1903C is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs
1
= 7.2kHz, Fsys = 4608 * Fs = 33.1776MHz and sclk = Fsys / 18 = 1.8432MHz.
2. If Fs
2
= 8.0kHz, Fsys = 4608 * Fs = 36.8640MHz and sclk = Fsys / 18 = 2.048MHz.
3. If Fs
3
= 9.6kHz, Fsys = 4608 * Fs = 44.2368MHz and sclk = Fsys / 18 = 2.4576MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting bit 7 in
control register 0Eh. The transition should be forced on or after the second Frame Synch period following
the write to a designated PLL programming register (0Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
During the normal operation, a data frame sync signal (FS) is generated by the 73M1903C at the rate of
Fs. For every data
FS
there are 16 bits transmitted and 16 bits received.
Page: 5 of 45
©
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
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