MX25L1608D
MX25L3208D
MX25L6408D
FEATURES
16M-BIT [x 1 / x 2] CMOS SERIAL FLASH
32M-BIT [x 1 / x 2] CMOS SERIAL FLASH
64M-BIT [x 1 / x 2] CMOS SERIAL FLASH
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
•
16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure
32M:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure
64M:67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O read mode) structure
• 512 Equal Sectors with 4K byte each (16Mb)
1024 Equal Sectors with 4K byte each (32Mb)
2048 Equal Sectors with 4K byte each (64Mb)
- Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each (16Mb)
64 Equal Blocks with 64K byte each (32Mb)
128 Equal Blocks with 64K byte each (64Mb)
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock
- Serial clock of two I/O read mode : 50MHz, which is equivalent to 100MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 60ms(typ.) /sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip
for 16Mb, 25s(typ.) for 32Mb, and 50s(typ.) for 64Mb
• Low Power Consumption
- Low active read current: 25mA(max.) at 86MHz, and 10mA(max.) at 33MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
- Deep power-down mode 1uA (typical)
• Typical 100,000 erase/program cycles
• 20 years of data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instruc-
tions
- Additional 512-bit secured area for unique identifier
• Auto Erase and Auto Program Algorithm
-
Automatically erases and verifies data at selected sector
-
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1505
1
REV. 1.0, AUG. 28, 2009
MX25L1608D
MX25L3208D
MX25L6408D
•
Status Register Feature
•
Electronic Identification
-
JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- Both REMS and REMS2 commands for 1-byte manufacturer ID and 1-byte device ID
HARDWARE FEATURES
•
SCLK Input
-
Serial clock input
• SI Input
-
Serial Data Input
• SO Output
-
Serial Data Output
• WP#/ACC pin
-
Hardware write protection and program/erase acceleration
• HOLD# pin
-
pause the chip without diselecting the chip
• PACKAGE
-
16-pin SOP (300mil)
*- 8-land WSON (8x6mm or 6x5mm)
-
8-pin SOP (200mil, *150mil)
*
-
8-pin PDIP (300mil)
*- 8-land USON (4x4mm)
-
All Pb-free devices are RoHS Compliant
* Advanced Information
GENERAL DESCRIPTION
The MX25L1608D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When
it is in two I/O read mode, the structure becomes 8,388,608 bits x 2. The MX25L3208D are 33,554,432 bit serial
Flash memory, which is configured as 4,194,304 x 8 internally. When it is in two I/O read mode, the structure be-
comes 16,772,216 bits x 2. The MX25L6408D are 67,108,864 bit serial Flash memory, which is configured as 8,388,608
x 8 internally. When it is in two I/O read mode, the structure becomes 33,554,432 bits x 2. (please refer to the "Two
I/O Read mode" section). The MX25L1608D/3208D/6408D feature a serial peripheral interface and software proto-
col allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI),
and a serial data output (SO). Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in-
put and data output.
The MX25L1608D/3208D/6408D provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte),
or block (64K-byte), or whole chip basis.
P/N: PM1505
2
REV. 1.0, AUG. 28, 2009
MX25L1608D
MX25L3208D
MX25L6408D
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC cur-
rent.
The MX25L1608D/3208D/6408D utilizes Macronix's proprietary memory cell, which reliably stores memory con-
tents even after typical 100,000 program and erase cycles.
Table 1. Additional Feature Comparison
Additional
Features
Part
Name
MX25L1608D
MX25L3208D
MX25L6408D
Protection and Security
Flexible Block
512-bit
Protection
Secured Area
(BP0-BP3)
V
V
V
V
V
V
Read
Performance
2 I/O Read
(50MHz)
V
V
V
Identifier
Device ID
Device ID
Device ID
(command: AB (command: 90 (command: EF
hex)
hex)
hex)
C2 14 (hex)
C2 14 (hex)
14 (hex)
(if ADD=0)
(if ADD=0)
C2 15 (hex)
C2 15 (hex)
15 (hex)
(if ADD=0)
(if ADD=0)
C2 16 (hex)
C2 16 (hex)
16 (hex)
(if ADD=0)
(if ADD=0)
RDID
(command: 9F
hex)
C2 20 15 (hex)
C2 20 16 (hex)
C2 20 17 (hex)
P/N: PM1505
3
REV. 1.0, AUG. 28, 2009
MX25L1608D
MX25L3208D
MX25L6408D
PIN CONFIGURATIONS
16-PIN SOP (300mil)
HOLD#
VCC
NC
NC
NC
NC
CS#
SO/SIO1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/ACC
8-PIN SOP (200mil, 150mil)
CS#
SO/SIO1
WP#/ACC
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
8-LAND WSON (8x6mm, 6x5mm), USON (4x4mm)
8-PIN PDIP (300mil)
CS#
SO/SIO1
WP#/ACC
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
CS#
SO/SIO1
WP#/ACC
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
PACKAGE OPTIONS
150mil 8-SOP
200mil 8-SOP
300mil 16-SOP
300mil 8-PDIP
6x5mm WSON
8x6mm WSON
4x4mm USON
16M
V
V
V
V
V
V
32M
V
V
V
V
V
64M
V
PIN DESCRIPTION
SYMBOL DESCRIPTION
Chip Select
Serial Data Input (for 1 x I/O)/ Serial Data
SI/SIO0
Input & Output (for 2xI/O read mode)
Serial Data Output (for 1 x I/O)/ Serial Data
SO/SIO1
Input & Output (for 2xI/O read mode)
SCLK Clock Input
Write protection: connect to GND ; 9.5~10.5V
WP#/ACC for program/erase acceleration: connect to
9.5~10.5V
Hold, to pause the device without
HOLD#
deselecting the device
VCC
+ 3.3V Power Supply
GND Ground
CS#
V
P/N: PM1505
4
REV. 1.0, AUG. 28, 2009
MX25L1608D
MX25L3208D
MX25L6408D
BLOCK DIAGRAM
Address
Generator
X-Decoder
Memory Array
Page Buffer
SI/SIO0
SO/SIO1
Data
Register
Y-Decoder
SRAM
Buffer
Mode
Logic
State
Machine
Sense
Amplifier
HV
Generator
CS#,
WP#/ACC,
HOLD#
SCLK
Clock Generator
Output
Buffer
P/N: PM1505
5
REV. 1.0, AUG. 28, 2009
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