2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5326/02
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A
B
C
D
E
F
G
H
1
BLE
I/O
8
I/O
9
V
SS
V
DD
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
NC
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
NC
A
15
A
13
A
10
5
A
2
CS
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
DD
V
SS
I/O
6
I/O
7
NC
5326 tbl 02a
FBGA (BF48-1)
Top View
Pin Description
A
0
– A
15
Address Inputs
Chip Select
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
2.5V Power
Ground
Input
Input
Input
Input
Input
Input
I/O
Power
Gnd
5326 tbl 01
TSOP
Top View
CS
WE
OE
BHE
BLE
I/O
0
– I/O
15
V
DD
V
SS
Truth Table
(1)
CS
H
L
L
L
L
L
L
L
L
OE
X
L
L
L
X
X
X
H
X
WE
X
H
H
H
L
L
L
H
X
BLE
X
L
H
L
L
L
H
X
H
BHE
X
H
L
L
L
H
L
X
H
I/O
0
-I/O
7
High-Z
DATA
OUT
High-Z
DATA
OUT
DATA
IN
DATA
IN
High-Z
High-Z
High-Z
I/O
8
-I/O
15
High-Z
High-Z
DATA
OUT
DATA
OUT
DATA
IN
High-Z
DATA
IN
High-Z
High-Z
Function
Deselected – Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
5326 tbl 02
6.42
2
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
DD
V
IN
, V
OUT
T
BIAS
T
STG
P
T
I
OUT
Rating
Supply Voltage Relative
to V
SS
Terminal Voltage Relative
to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–0.3 to +3.6
–0.3 to V
DD
+0.3
–55 to +125
–55 to +125
1.25
50
Unit
V
V
o
o
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
SS
0V
0V
V
DD
See Below
See Below
5326 tbl 04
C
C
W
mA
Recommended DC Operating
Conditions
Symbol
V
DD
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.375
0
1.7
–0.3
(2)
Typ.
2.5
0
____
____
Max.
2.625
0
V
DD
+0.3
(1)
0.7
Unit
V
V
V
V
5326 tbl 03
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
Unit
pF
pF
5326 tbl 05
NOTES:
1. V
IH
(max) = V
DD
+ 1.0V a.c. (pulse width less than t
CYC
/2) for I < 20 mA, once
per cycle.
2. V
IL
(min) = -1.0V a.c. (pulse width less than t
CYC
/2) for I < 20 mA, once per cycle.
5326 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
DC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71T016SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
DD
= Max., V
IN
= V
SS
to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= V
SS
to V
DD
I
OL
= 2.0mA, V
DD
= Min.
I
OH
= 2.0mA, V
DD
= Min.
Min.
___
Max.
5
5
0.7
___
Unit
µA
µA
V
V
5326 tbl 07
___
___
1.7
DC Electrical Characteristics
(1,2)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
– 0.2V)
71T016SA10
Parameter
Symbol
I
CC
Dynamic Operating Current
CS
< V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
Dynamic Standby Power Supply Current
CS
> V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
Full Standby Power Supply Current (static)
CS
> V
HC
, Outputs Open, V
DD
= Max., f = 0
(3)
Max.
Typ.
(4)
Com'l
160
90
45
10
Com'l
150
85
40
15
Ind
160
____
71T016SA12
71T016SA15
Com'l
130
80
35
15
Ind
130
____
71T016SA20
Com'l
120
80
30
15
Ind
120
mA
____
Unit
I
SB
I
SB1
45
15
35
15
30
15
mA
mA
NOTES:
5326 tbl 8
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
– 0.2V (High).
3. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing .
4. Typical values are measured at 2.5V, 25°C and with equal read and write cycles. This parameter is guaranteed by device characterization but is not production
tested.
6.42
3
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
0V to 2.5V
1.5ns
(V
DD
/2)
(V
DD
/2)
See Figure 1, 2 and 3
5326 tbl 09
AC Test Loads
+1.25V
50Ω
I/O
Z
0
= 50Ω
30pF
5326 drw 03
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
Figure 3. Output Capacitive Derating
6.42
4
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
71T016SA10
(2)
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
BE
t
BLZ
(1)
t
BHZ
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select Hig h to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
10
____
____
71T016SA12
Min.
Max.
71T016SA15
Min.
Max.
71T016SA20
Min.
Max.
Unit
Parameter
Min.
Max.
12
____
____
15
____
____
20
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
____
12
12
____
15
15
____
20
20
____
____
____
____
____
4
____
4
____
5
____
5
____
5
5
____
6
6
____
6
7
____
8
8
____
____
____
____
____
0
____
0
____
0
____
0
____
5
—
5
____
6
—
6
____
6
—
7
____
8
—
8
____
4
—
0
____
4
—
0
____
4
—
0
____
4
____
0
____
5
6
6
8
WRITE CYCLE
t
WC
t
AW
t
CW
t
BW
t
AS
t
WR
t
WP
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
Address Ho ld from End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
10
7
7
7
0
0
7
5
0
3
____
____
12
8
8
8
0
0
8
6
0
3
____
____
15
10
10
10
0
0
10
7
0
3
____
____
20
12
12
12
0
0
12
9
0
3
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5326 tbl 10
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
5
6
6
8
NOTES:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
