DATASHEET
PLL AUDIO CLOCK SYNTHESIZER
Description
The MK2703 is a low-cost, low-jitter, high-performance PLL
clock synthesizer designed to replace oscillators and PLL
circuits in set-top box and multimedia systems. Using IDT’s
patented analog Phase Locked Loop (PLL) techniques, the
device uses a 27 MHz crystal or clock input to produce a
buffered reference clock and a selectable audio clock.
IDT manufactures the largest variety of Set-Top Box and
multimedia clock synthesizers for all applications. Consult
IDT to eliminate VCXOs, crystals and oscillators from your
board.
MK2703
Features
•
•
•
•
•
•
•
•
•
•
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Uses an inexpensive, fundamental mode crystal or clock
Supports MPEG sampling rates of 32 kHz, 44.1 kHz, 48
kHz, and 96 kHz
Patented zero ppm synthesis error in all clocks
All frequencies are frequency locked
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3 V or 5 V
Industrial temperature version available
The MK2703B is recommended for new designs
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
VDD
S1:0 2
PLL Clock
Synthesis
and Control
Circuitry
Crystal
Oscillator
Audio Clock
X1
27 MHz
crystal or
clock input
27M
X2
Capacitors are required for crystal tuning
GND
IDT™
PLL AUDIO CLOCK SYNTHESIZER
1
MK2703
REV J 122109
MK2703
PLL AUDIO CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Pin Assignment
X1
VDD
GND
27M
1
2
3
4
8
7
6
5
X2
S0
S1
CLK
A
UDIO
C
LOCK
O
UTPUT
S
ELECT
T
ABLE
S1
0
0
1
1
S0
0
1
0
1
CLK (MHz)
8.192
11.2896
12.288
24.576
Key: 0 = Connect pin directly to ground
8-pin (150 mil) SOIC
1 = Connect pin directly to VDD
Pin Descriptions
Pin
Pin
Number Name
1
2
3
4
5
6
7
8
X1
VDD
GND
27M
CLK
S1
S0
X2
Pin
Type
XI
Power
Power
Output
Output
Input
Input
XO
Connect to +3.3 V or +5 V.
Connect to ground.
Pin Description
Crystal Connection. Connect to a 27 MHz fundamental crystal or clock.
27 MHz buffered reference clock output.
Audio clock output per table above.
Audio clock frequency select input #1. Determines CLK output per table
above. Internal pull-up resistor.
Audio clock frequency select input #0. Determines CLK output per table
above. Internal pull-up resistor.
Crystal connection to a 27 MHz crystal, or leave unconnected for clock
output.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the MK2703
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 2 and 3. It must be
connected close to the MK2703 to minimize lead
inductance. No external power supply filtering is required for
the MK2703.
Series Termination Resistor
A 33Ω terminating resistor can be used next to the clock
outputs for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 16 pF. A
parallel resonant, fundamental mode, AT cut 27 MHz crystal
should be used. The device crystal connections should
include pads for small capacitors from X1 to ground and
from X2 to ground. These capacitors are used to adjust the
IDT™
PLL AUDIO CLOCK SYNTHESIZER
2
MK2703
REV J 122109
MK2703
PLL AUDIO CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming process,
it is important to keep stray capacitance to a minimum by
using very short PCB traces (and no vias) between the
crystal and device. Crystal capacitors, if needed, must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-16
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with an 18 pF load capacitance, each
crystal capacitor would be 4 pF [(18-16) x 2] = 4.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2703. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, MK2703S (commercial)
Ambient Operating Temperature, MK2703SI (industrial)
Storage Temperature
Soldering Temperature
-0.5 V to 7 V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.13
Typ.
Max.
+85
+5.50
Units
°
C
V
DC Electrical Characteristics
VDD=3.3 V ±5%
, Ambient temperature -40 to +85° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
Conditions
X1 pin only
Note 1
X1 pin only
Note 1
S0, S1 pins
S0, S1 pins
I
OH
= -12 mA
Min.
3.13
Typ.
Max.
5.50
Units
V
V
V
V
(VDD/2)+1 VDD/2
VDD/2 (VDD/2)-1
2.0
0.8
2.4
V
V
IDT™
PLL AUDIO CLOCK SYNTHESIZER
3
MK2703
REV J 122109
MK2703
PLL AUDIO CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Parameter
Output Low Voltage
Output High Voltage, CMOS level
Operating Supply Current
Short Circuit Current
Input Capacitance
Nominal Output Impedance
Frequency Synthesis Error
Internal Pull-up Resistor
Symbol
V
OL
V
OH
IDD
Conditions
I
OL
= 12 mA
I
OH
= -4 mA
No load
VDD = 3.3 V
CLK output
S0, S1 pins
All Clocks
Min.
VDD-0.4
Typ.
Max.
0.4
Units
V
V
mA
mA
pF
Ω
25
+50
5
20
0
500
C
IN
ppm
kΩ
R
PUP
S1, S0 pins
Note 1: CMOS level input. Nominal trigger point is VDD/2 for 3.3 V or 5 V operation.
AC Electrical Characteristics
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Input Crystal or Clock Frequency
Output Clock Rise Time
Output Clock Fall Time
Clock Stabilization Time after
Power-up
Changing Frequency Setting
Output Clock Duty Cycle
Maximum Absolute Jitter, short
term
Note 1: Measured with 15 pF load.
Symbol
F
IN
t
OR
t
OF
Conditions
0.8 to 2.0 V, Note 1
2.0 to 8.0 V, Note 1
Min.
Typ.
27
Max.
1.5
1.5
10
10
Units
MHz
ns
ns
ms
ms
%
ps
at VDD/2, Note 1
t
ja
Deviation from
mean
40
±190
60
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
150
140
120
40
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™
PLL AUDIO CLOCK SYNTHESIZER
4
MK2703
REV J 122109
MK2703
PLL AUDIO CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Marking Diagram - MK2703S
Marking Diagram - MK2703SI
MK2703I
######
YYWW$$
µCLOCK
MK2703S
YYWW
Bottom Marking:
Line 1: ######
Line 2 & 3: Origin
Bottom Marking:
Origin
Marking Diagram - MK2703SLF
µCLOCK
MK2703SL
YYWW
Marking Diagram - MK2703SILF
Bottom Marking:
Line 1: ######
Line 2 & 3: Origin
MK2703IL
######
YYWW$$
Bottom Marking:
Origin
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and the week number that the part was assembled.
3. Bottom mark denotes country of origin.
IDT™
PLL AUDIO CLOCK SYNTHESIZER
5
MK2703
REV J 122109
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
