Preliminary Data Sheet, DS3, July 2003
DuSLIC
Dual Channel Subscriber Line
Interface Concept
PEB 3264, Version 1.4
PEB 3265, Version 1.5
PEB 4264/-2, Version 1.1/1.2
PEB 4364, Version 1.1/1.2
PEB 4265/-2, Version 1.1/1.2
PEB 4365, Version 1.2
PEB 4266, Version 1.2
Wired
Communications
N e v e r
s t o p
t h i n k i n g .
ABM
®
, ACE
®
, AOP
®
, ARCOFI
®
, ASM
®
, ASP
®
, DigiTape
®
, DuSLIC
®
, EPIC
®
, ELIC
®
,
FALC
®
, GEMINAX
®
, IDEC
®
, INCA
®
, IOM
®
, IPAT
®
-2, ISAC
®
, ITAC
®
, IWE
®
, IWORX
®
,
MUSAC
®
, MuSLIC
®
, OCTAT
®
, OptiPort
®
, POTSWIRE
®
, QUAT
®
, QuadFALC
®
,
SCOUT
®
, SICAT
®
, SICOFI
®
, SIDEC
®
, SLICOFI
®
, SMINT
®
, SOCRATES
®
, VINETIC
®
,
10BaseV
®
, 10BaseVX
®
are registered trademarks of Infineon Technologies AG.
10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG.
Microsoft
®
is a registered trademark of Microsoft Corporation. Linux
®
is a registered
trademark of Linus Torvalds.
The information in this document is subject to change without notice.
Edition 2003-07-11
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
©
Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide
(www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Preliminary Data Sheet
Revision History:
Previous Version: DS2
Page
Title
all
all
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all
Page 18
Page 23
Page 25
Page 32
Page 33
Page 38
Page 42
Page 50
Subjects (major changes since last revision)
Product name corrected to
Dual Channel Subscriber Line Interface
Concept
PEB 3265 version changed from 1.2 to 1.5
PEB 4264/-2 and PEB 4265/-2: version 1.2 added
PEB 4266 version changed from 1.1 to 1.2
PEB 3264 version changed from 1.2 to 1.4
Bit VRTLIM renamed to VTRLIM
Bit VRTLIM-M renamed to VTRLIM-M
New SLICs TSLIC-E and TSLIC-S added
New SLICOFI-2 (Version 1.5 only) package P-TQFP-64-1 added
New package P-VQFN-48-4 for SLIC-S/-S2, SLIC-E/-E2 and SLIC-P
added
Former chapter 2 "Pin Descriptions" removed. See updated device data
sheets.
“Overview” on Page 18:
Chapter reworked, tables for codec and SLIC
chips added.
“Features” on Page 23:
ITU-T Recommendation G.712 added
“Logic Symbols” on Page 25:
Logic symbol for SLIC-E/-E2 Version 1.2
added.
“Block Diagram SLICOFI-2/-2S” on Page 32:
block diagrams of SLIC
devices removed.
Figure 10 "Signal Paths – DC Feeding" on Page 33:
C
ITA
(
C
ITB
) renamed
to
C
ITACA
(
C
ITACB
).
Table 4 "DC Characteristics" on Page 38:
V
LIM
changed from 50 V to 72
V.
Figure 19 "Signal Paths – AC Transmission" on Page 42:
C
ITA
(
C
ITB
)
renamed to
C
ITACA
(
C
ITACB
).
“Internal Balanced Ringing via SLICs” on Page 50:
V
DROP,RT
renamed to
V
DROP,TR
,
V
RT,RMS
renamed to
V
TR,RMS
,
V
RT0,RMS
renamed to
V
TR0,RMS
Figure 30 "Bellcore On-Hook Caller ID Physical Layer Transmission"
on Page 61:
note added.
“Caller ID Buffer Handling of SLICOFI-2” on Page 61:
description for
listing item (9) changed
“Non Linear Processor (NLP) in DuSLIC-E/-E2/-P” on Page 64
added.
2003-07-11
DS3
Page 61
Page 61
Page 64
Page 66
Page 68
Page 84
Page 85
Page 86
Page 88
Page 90
Page 94
Page 94
Page 97
Page 99
Page 101
Page 113
Page 116
“MIPS Requirements for EDSP Capabilities” on Page 66
updated with
NLP examples.
“Three-party Conferencing in DuSLIC-E/-E2/-P” on Page 68:
sentence
about Multi-party Conferencing added
“Hardware and Power On Reset” on Page 84:
reset routine duration
changed to 1.5 ms.
Figure 36 "DuSLIC Reset Sequence" on Page 85:
textual description
changed.
Table 17, “Default DC and AC Values” on Page 86:
L
X
and L
R
changed.
“Recommended Procedure for Reading the Interrupt Registers” on
Page 88
added.
“Power Management and Operating Modes” on Page 90:
Power
dissipation values and description updated.
“Integrated Test and Diagnostic Functions (ITDF)” on Page 94:
ITDF
is now also available for SLICOFI-2S.
Figure 3.8.1.2 "DuSLIC Line Testing" on Page 94:
description on line
testing capability modified.
“Using the Level Metering Integrator” on Page 97:
timing for LM-OK bit
added.
Figure 44, “Timing LM-OK Bit” on Page 99:
1 ms delay time for
SLICOFI-2 Version 1.5 added.
Table 20 "KINTDC Setting Table" on Page 101:
description about
DuSLICOS settings added below.
“Capacitance Measurements” on Page 113:
note on offset calibration
added at the end of the chapter.
“Line Capacitance Measurements Ring and Tip to GND” on Page 116:
description of last list item in section "Calculating parameter values"
modified, description in table of section "Program Sequence" modified
Chapter 4.2.3, Operation with IOM-2 TE Devices (1.536 MHz)
added.
“TIP/RING Interface” on Page 139:
content removed - see device data
sheets for detailed information.
“SOP Command” on Page 144:
note on empty register bits added
Register
XCR:
Description for bit ASYNCH-R changed
Register
INTREG1,
bits HOOK and GNDK: description changes
Register
INTREG2:
reset value changed from 20
H
to 4F
H
, description for bit
RSTAT modified
Register
BCR1,
bit SLEEP-EN: note added
Register
BCR2:
description added fot bits UTDX-SRC and PDOT-DIS
Register
BCR5,
bit DTMF-SRC: description added
Register
DSCR,
bit PTG: description added
“COP Command” on Page 203:
note on empty register bits added
Page 137
Page 139
Page 144
Page 151
Page 152
Page 154
Page 167
Page 170
Page 177
Page 179
Page 203
Page 205
Page 207
Page 207
Page 208
Page 213
Page 233
Page 248
Page 258
Page 266
Page 273
Page 278
Page 278
Page 287
Page 295
Page 297
Page 299
Page 301
Page 315
Page 318
Page 325
Page 326
Page 331
Page 342
Page 344
Table 35 "CRAM Coefficients" on Page 205:
TTX Slope extended by
nibbles 6 and 7
“POP Command” on Page 207:
note on the necessity of immediate
programming added
“Sequence for POP Register Programming” on Page 207
added
(because added NLP coefficients)
“POP Register Overview” on Page 208:
NLP coefficients added
“POP Register Description” on Page 213:
NLP coefficients added
Table 53 "Range of DeltaPLEC" on Page 233:
"0x80 - no detection"
added.
Register
CIS/LEC-MODE:
description added for bit UTDX-SUM and note
on bit 3 added.
“Recommended NLP Coefficients” on Page 258
added
“SOP Command” on Page 266:
note on empty register bits added
Register XCR: Description for bit ASYNCH-R changed
Register
LMRES1:
bits added.
Register
LMRES2:
bits added.
Register
BCR1:
bits added.
Register
DSCR,
bit PTG: description added
Register
LMCR1:
bits added.
Register
LMCR2:
bits added.
Register
LMCR3:
bits added.
“COP Command” on Page 315:
note on empty register bits added
Table 73 "CRAM Coefficients" on Page 318:
TTX slope extended by
nibbles 6 and 7
“Electrical Characteristics” on Page 325:
SLIC and
SLICOFI-2x
data
removed - for detailed information see device data sheets.
Table 76, “AC Transmission” on Page 326:
Symbol
V
RT
renamed to
V
TR
AC Transmission Characteristics: Values for Distortion and associated
figures changed
“Input/Output Waveform for AC Tests” on Page 342
added.
PCM interface timings
“Single-Clocking Mode” on Page 344
and
“Double-Clocking Mode” on Page 346:
FSC hold time (t
FSC_h
) renamed to FSC hold time 1 (t
FSC_h1
),
FSC hold time 2 (t
FSC_h2
) added, formula of max. value for TCA/B delay
time off (
t
dTCoff
) modified
IOM-2 interface timings
“Single-Clocking Mode” on Page 349
and
“Double-Clocking Mode” on Page 351:
FSC hold time (t
FSC_h
) renamed to FSC hold time 1 (t
FSC_h1
),
FSC hold time 2 (t
FSC_h2
) added, parameters and timing of pin DU modified
Period PCLK (
t
PCLK
) for double clocking: formula for typ. value modified.
Page 349
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