Edition 04.2001
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 4/9/01.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
PEB 20256 E
PEF 20256 E
Revision History:
04.2001
Previous Version:
Preliminary Data Sheet 11.1999
Major changes to document since last version
Page
25
26
54
154
155
159
190
203
205
206
207
210
211
Description
Pin Diagram added 16-Port mode
Pin Diagram added 28-Port mode
Remote payload loop block diagram redrawn
DS2
Swap the bit positions of TBRTC and TBFTC In the CSPEC_BUFFER
register as their bit postitions were not correct in the preliminary data sheet.
Swap the postions of TBRTC with TBFTC in Table 8-7, as their column
positions were not correct in the preliminary data sheet
Fixed typo in CSPEC_IMASK register, replaced ROFD with RFOD
Fixed typo in IQMASK, replaced ROFD with RFOD
Update voltage min/max information for
Table 9-1 Absolute Maximum
Ratings
Update timing Information for
Table 9-4 DC Characteristics (PCI
Interface Pins)
Update timing Information for
Table 9-5 PCI Clock Characteristics
Update timing Information for
Table 9-6 PCI Interface Signal
Characteristics
Update timing Information for
Table 9-8 Intel Bus Interface Timing
Intel Bus Interface Timing Diagram modified. The setup and hold times for
“LD to LRDY” was not a valid timing parameter. Instead, the setup and hold
parameters for “LD to LRD” were specified.
Update timing Information for
Table 9-9 Intel Bus Interface Timing
(Master Mode)
Timing parameter (setup time) 67a was changed from “LD to LDRY” to ”LD
to LRD”, because it was not a valid timing parameter.
Timing parameter (hold time) 67b was changed from “LD to LDRY” to ”LD
to LRD”, because it was not a valid timing parameter.
Update timing Information for
Table 9-10 Motorola Bus Interface Timing
Update timing Information for
Table 9-11 Motorola Bus Interface Timing
(Master Mode)
213
213
213
215
218
Data Sheet
4
04.2001
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
