Edition 2001-11-16
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
PEF 20451 / 20471 / 24471
PRELIMINARY
Revision History:
2001-11-16
Previous Version:
PEF 20451 / 20471 / 24471 V1.2, Preliminary Data Sheet DS1, 2001-04-04
Page
20
35
43
49
68
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112
128
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144
146
Content
Table 6
updated
Chapter 3.4.4
updated, added
Figure 14
Chapter 3.7.1
and
Chapter 3.7.2
updated
Chapter 4.3
reworked
DS 1
Description of Configuration Command Register 1 and 2 (CMD1 and
CMD2)
updated
Description of Interrupt Status Register 1 (ISTA1) reworked
Description of Interrupt Error Status Register 1 and 2 (IESTA1 and
IESTA2)
reworked
Description of Interrupt Error Mask Register (INTEM2) reworked
Description of Source Address (SA) and Destination Address (DA)
Registers updated
Chapter 6.2
reworked
Chapter 6.8.3
reworked
Chapter 7.1
and
Table 27
“PCM timing” updated
Table 28
“PCM Parallel Mode Timing”
Table 35
and
Figure 57
updated
Added
Chapter 7.8, “Hardware Reset Timing”
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEF 20451 / 20471 / 24471
Table of Contents
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
3
3.1
3.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.3
3.3.1.4
3.3.1.5
3.3.1.6
3.3.1.7
3.3.2
3.3.3
3.3.4
3.4
3.4.1
3.4.2
3.4.2.1
3.4.2.2
3.4.3
3.4.4
3.4.5
Page
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Overview of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features in Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standard PBX or CO Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Computer Telephony Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Router / Remote Access Application . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voice over IP Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Bus Interface (PCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architectural Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum and Constant Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subchannel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multipoint Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Broadcast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stream-to-Stream Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Message Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Mode for Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Block Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analyze Connection and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog PLL (APLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter-Transfer-Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master-Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
16
16
19
19
20
20
21
22
23
23
24
25
25
25
25
25
26
26
27
29
29
30
30
31
31
32
33
34
35
35
36
Preliminary Data Sheet
2001-11-16
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