Edition 2001-11-20
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
PEF 20450 / 20470 / 24470
PRELIMINARY
Revision History:
2001-11-20
Previous Version:
PEF 20450 / 20470 / 24470 V1.2, Preliminary Data Sheet DS1, 2001-04-04
Page
12
26
28
30
49
57
58
60
74
82
85
101
104
110
112
115
Content
Table 5
updated
Chapter 3.4.3
updated, added
Figure 9
Chapter 3.7.1
and
Chapter 3.7.2
updated
Chapter 4.2
reworked
DS 1
Description of Configuration Command Register 1 and 2 (CMD1 and
CMD2)
updated
Description of Interrupt Status Register 1 (ISTA1) reworked
Description of Interrupt Error Status Register 1 and 2 (IESTA1 and
IESTA2)
reworked
Description of Interrupt Error Mask Register 1 and 2 (INTEM1 and
INTEM2)
reworked
Chapter 6.2
reworked
Figure 18
updated
Chapter 6.7.3
reworked
Chapter 7.1
and
Table 22
updated
Table 23
updated
Table 27
and
Figure 39
updated
Added
Chapter, 7.5“Hardware Reset Timing”
Table 32
updated.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEF 20450 / 20470 / 24470
Table of Contents
1
1.1
1.2
1.3
1.4
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
3
3.1
3.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.3
3.3.1.4
3.3.1.5
3.3.1.6
3.3.2
3.3.3
3.3.4
3.4
3.4.1
3.4.2
3.4.2.1
3.4.2.2
3.4.3
3.4.4
3.5
3.6
3.7
3.7.1
3.7.2
4
Page
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Overview of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features in Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standard PBX or CO Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Bus Interface (PCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architectural Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum and Constant Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subchannel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multipoint Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Broadcast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Message Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Mode for Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Block Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analyze Connection and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog PLL (APLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read SWITI Configuration with Indirect Register Addressing . . . . . . . . . .
Power-On and Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
12
12
12
13
13
14
15
15
16
17
17
17
17
17
18
18
19
19
20
20
21
21
22
23
25
26
27
27
27
28
28
28
Description of Interfaces
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2001-11-20
Preliminary Data Sheet
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
