MT9072
Octal T1/E1/J1 Framer
Data Sheet
Features
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Eight fully independent, T1/E1/J1 framers
3.3 V supply with 5 V tolerant inputs
Selectable 2.048 Mbit/s or 8.192 Mbit/s serial
buses for both data and signaling
Framing Modes:
- T1: D4, ESF, T1DM
- E1: Basic Framing, CRC4 multiframing and
Signaling Multiframing
Supports Inverse Mux for ATM
Timeslot assignable HDLC
IEEE-1149.1 (JTAG) test port
T1/E1/J1 add/drop multiplexers
V5.1 and V5.2 access network interfaces
CO and PBX equipment interfaces
Primary rate IDSN nodes
Ordering Information
MT9072AV
MT9072AV2
220 Pin PBGA
220 Pin PBGA**
Trays
Trays
August 2011
**Pb Free Tin/Silver/Copper
-40C to +85C
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Digital Cross-connect Systems (DCS)
Wireless base stations
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Description
The MT9072 is a multi-port T1/E1/J1 framing device
that integrates eight fully independent, feature rich
framers. The device is software selectable between T1,
E1 or J1 modes and meets the latest relevant
recommendations and standards from Telcordia, ANSI,
ETSI and ITU-T. An extensive suite of features make
the MT9072 very flexible and suitable for a wide variety
of applications around the globe.
Applications
TxDL[0] TxDLC[0]
DSTi [0]
CSTi [0]
TxCL [0]
TPOS[0]
TNEG[0]
ST-BUS
Interface
Transmit Framing, Error and
Test Signal Generation
Remote
Loopback
ST-BUS
Loopback
CKi[0]
FPi[0]
Payload
Loopback
National
Bit Buffer
ST-BUS
Data Link
Circuit
Timing
CAS
Buffer
Digital
Loopback
DSTo[0]
CSTo[0]
ST-BUS
Interface
Receive Framing, Performance Monitoring,
Alarm Detection, 2 Frame Slip Buffer
RxBF[0] EXCLi[0]
RPOS[0]
RNEG[0]
FRAMER 0
FRAMER 1
FRAMER 2
FRAMER 3
FRAMER 4
FRAMER 5
FRAMER 6
FRAMER 7
RxDLC[0] RxDL[0] RxMF[0]
Microprocessor Interface
IEEE 1149.1 TAP
Common Control and Power
D15~D0 A11~A0
DS RW CS
IRQ
IM
TDI TDO TMS TCK TRST RESET TAIS VDD VSS T1-3
TxMF
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2011, Zarlink Semiconductor Inc. All Rights Reserved.
MT9072
1.0
Change Summary
Data Sheet
Changes from the November 2005 Issue to the August 2011 Issue.
Page
1
Item
Ordering Information
Change
Obsoleted 208L LQFP package.
Changes from March 2004 Issue to October 2004 Issue.
Page
242
Item
“Recommended Operating
Conditions” Table.
Change
Corrected Min. value to 3.0.
2
Zarlink Semiconductor Inc.
MT9072
MT9072 Detailed Feature Summary
Standards Compliance and Support
T1/J1 Mode
ANSI:
T1.102, T1.231
T1.403, T1.408
AT&T:
TR 62411, PUB43801
Telcordia:
GR-303-CORE
ITU-T:
G.802
TTC:
JT-G703, JT-G704
JT-G706
Access and Control
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ITU-T:
G.703, G.704, G.706, G.711, G.732
G.775, G.796, G.823, I.431
G.965 (V5.2)
ETSI:
TBR4, TBR13
ETS 300 233, ETS 300 347 (V5.2)
E1 Mode
Data Sheet
A 16-bit parallel Motorola or Intel non-multiplexed microprocessor interface is used to access the control and
status registers
Backplane Interfaces
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2.048 Mbit/s or 8.192 Mbit/s ST-BUS
2.048 Mbit/s GCI bus
IMA (Inverse Mux for ATM) mode, 1.544 Mbit/s (T1) or 2.048 Mbit/s (E1) serial bus with asynchronous
transmit and receive timing for Inverse MUX for ATM applications.
CSTo/CSTi pins can be used to access the receive/transmit signaling data
RxDL pin can be used to access the entire B8ZS/HDB3 decoded receive stream including framing bits
TxDL pin can be used to transmit data on the FDL (T1) or the Sa bits (E1)
T1/J1 Mode
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PCM24 channels 1-24 are mapped to ST-BUS
channels 0-23 respectively
The framing-bit is mapped to ST-BUS channel
31
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E1 Mode
PCM30 timeslots 0-31 are mapped to ST-BUS
channels 0-31 respectively
3
Zarlink Semiconductor Inc.
MT9072
Data Link
T1/J1 Mode
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Three methods are provided to access the
datalink:
1. TxDL and RxDL pins support transmit and
receive datalinks
2. Bit Oriented Messages are supported via
internal registers
3. An internal HDLC can be assigned to
transmit/receive over the FDL in ESF mode
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E1 Mode
Data Sheet
Two methods are provided to access the
datalink:
1. TxDL and RxDL pins support transmit and
receive datalinks over the Sa4~Sa8 bits
2. An internal HDLC can be assigned to
transmit/receive data via the Sa4~Sa8 bits
In transparent mode, if the Sa4 bit is used for
an intermediate datalink, the CRC-4 remainder
can be updated to reflect changes to the Sa4
bit
One Embedded Floating HDLC per Framer
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Flag generation and Frame Check Sequence (FCS) generation and detection, zero insertion and deletion
Continuous flags, or continuous 1s are transmitted between frames
Transmit frame-abort
Invalid frame handling:
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Frames yielding an incorrect FCS are tagged as bad packets
Frames with fewer than 25 bits are ignored
Frames with fewer than 32 bits between flags are tagged as bad packets
Frames interrupted by a Frame-Abort sequence remain in the FIFO and an interrupt is generated
Access is provided to the receive FCS
FCS generation can be inhibited for terminal adaptation
Recognizes single byte, dual byte and all call addresses
Independent, 32 byte deep transmit and receive FIFOs
Receive FIFO maskable interrupts for nearly full and overflow conditions
Transmit FIFO maskable interrupts for nearly empty and underflow conditions
Maskable interrupts for transmit end-of–packet and receive end-of-packet
Maskable interrupts for receive bad-frame (includes frame abort)
Transmit-to-receive and receive-to-transmit loopbacks are provided
Transmit and receive bit rates and enables are independent
Frame aborts can be sent under software control and they are automatically transmitted in the event of a
transmit FIFO underrun
4
Zarlink Semiconductor Inc.
MT9072
T1/J1 Mode
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Assignable to the ESF Facility Data Link or any
other channel
Operates at 4 kbit/s (FDL), 56 kbit/s or
64 kbit/s
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E1 Mode
Data Sheet
Assignable to timeslot-0, bits Sa4~Sa8 or any
other timeslot
Operates at 4, 8, 12, 16 or 20 kbit/s (Sa bits)
or 64 kbit/s
Common Channel Signaling Timeslot Assigner
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Selected 64 Kbit/s CCS channels (for V5.2 and GR-303) can be routed to/from an external multichannel
HDLC, using the CSTi/0 pins
Access and Monitoring for National (Sa) Bits (E1 mode only)
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In addition to the datalink functions, the Sa bits can be accessed using:
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Single byte register
Five byte transmit and receive national bit buffers
A maskable interrupt is generated on the change of state of any Sa bit
Slip Buffers
T1/J1 Mode
Transmit Slip Buffer
• Two-frame slip buffer capable of performing a
controlled slip. Intended for rate conversion in
the transmit direction
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Programmable delay
Transmit slips are independent of receive slips
Indication of slip
Indication of slip direction
E1 Mode
Receive Slip Buffer
• Two-frame slip buffer capable of performing a
controlled slip
• Wander tolerance of 208 UI peak-to-peak
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Indication of slip
Indication of slip direction
Receive Slip Buffer
• Two-frame slip buffer capable of performing a
controlled slip
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Wander tolerance of 142 UI (92
s)
peak
Indication of slip
Indication of slip direction
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