MT9042C
Multitrunk System Synchronizer
Data Sheet
Features
•
Meets jitter requirements for: AT&T TR62411
Stratum 3, 4 and Stratum 4 Enhanced for DS1
interfaces; and for ETSI ETS 300 011, TBR 4,
TBR 12 and TBR 13 for E1 interfaces
Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
Provides 8 kHz ST-BUS framing signals
Selectable 1.544 MHz, 2.048 MHz or 8 kHz
input reference signals
Accepts reference inputs from two independent
sources
Provides bit error free reference switching -
meets phase slope and MTIE requirements
Operates in either Normal, Holdover and
Freerun modes
Ordering Information
MT9042CP
MT9042CPR
MT9042CP1
MT9042CPR1
28
28
28
28
Pin
Pin
Pin
Pin
PLCC
PLCC
PLCC*
PLCC*
Tubes
Tape & Reel
Tubes
Tape & Reel
November 2005
•
•
•
•
•
•
*Pb Free Matte Tin
-40°C to +85°C
Description
The MT9042C Multitrunk System Synchronizer
contains a digital phase-locked loop (DPLL), which
provides timing and synchronization signals for
multitrunk T1 and E1 primary rate transmission links.
The MT9042C generates ST-BUS clock and framing
signals that are phase locked to either a 2.048 MHz,
1.544 MHz, or 8 kHz input reference.
The MT9042C is compliant with AT&T TR62411
Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300 011.
It will meet the jitter tolerance, jitter transfer, intrinsic
jitter, frequency accuracy, holdover accuracy, capture
range, phase slope and MTIE requirements for these
specifications.
VDD
VSS
Applications
•
•
•
Synchronization and timing control for
multitrunk T1 and E1 systems
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
TRST
OSCi
OSCo
Master
Clock
TIE
Corrector
Circuit
Virtual
Refer-
ence
DPLL
Output
Interface
Circuit
State
Select
Input
Impairment
Monitor
Feedback
Guard Time
Circuit
Frequency
Select
MUX
PRI
SEC
Reference
Select
MUX
Reference
Selected
Refer-
ence
TIE
Correcto
r Enable
C1.5o
C3o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
State
Select
RSEL
LOS1
LOS2
Automatic/Manual
Control State Machine
MS1
MS2
RST
GTo
GTi
FS1
FS2
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
MT9042C
Change Summary
Data Sheet
Changes from November 2004 Issue to November 2005 Issue. Page, section, figure and table numbers refer to this
issue.
Page
4
Item
Pin Description - Pin 28 RST
Change
The sentence "While the RST pin is low, all
frame and clock outputs are at logic high." is
changed to "While the RST pin is low, all
frame and all clock outputs except C16o are at
logic high; C16o is at logic low."
Changes from July 2004 Issue to November 2004 Issue. Page, section, figure and table numbers refer to this issue.
Page
18
24
Item
Guard Time Calculation
Table "DC Electrical Characteristics"
line item 7
Change
Example time increases from to 0.9 to1.45
seconds.
Changed Minimum Schmitt high level input
voltage V
SIH
from 2.3 volts to 3.4 volts.
2
Zarlink Semiconductor Inc.
MT9042C
Data Sheet
VDD
OSCo
OSCi
F16o
F0o
F8o
C1.5o
4 3 2 1 28 27 26
5
25
24
6
23
7
22
8
21
9
20
10
19
11
12 13 14 15 16 17 18
TRST
VSS
RST
FS1
FS2
RSEL
MS1
MS2
LOS1
LOS2
GTo
GTi
Figure 2 - Pin Connections
Pin Description
Pin #
1,15
2
Name
V
SS
TRST
Ground.
0 Volts.
TIE Circuit Reset (TTL Input).
A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a re-alignment of input phase with output phase as shown in
Figure 19. The TRST pin should be held low for a minimum of 300 ns.
Secondary Reference (TTL Input).
This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of three possible frequencies (8 kHz, 1.544 MHz,
or 2.048 MHz) may be used. The selection of the input reference is based upon the MS1,
MS2, LOS1, LOS2, RSEL, and GTi control inputs (Automatic or Manual).
Primary Reference (TTL Input).
See pin description for SEC.
Positive Supply Voltage.
+5V
DC
nominal.
Oscillator Master Clock (CMOS Output).
For crystal operation, a 20 MHz crystal is
connected from this pin to OSCi, see Figure 10. For clock oscillator operation, this pin is left
unconnected, see Figure 9.
Oscillator Master Clock (CMOS Input).
For crystal operation, a 20 MHz crystal is
connected from this pin to OSCo, see Figure 10. For clock oscillator operation, this pin is
connected to a clock source, see Figure 9.
Frame Pulse ST-BUS 16.384 Mb/s (CMOS Output).
This is an 8 kHz 61 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 16.384 Mb/s. See Figure 20.
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output).
This is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 20.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output).
This is an 8 kHz 122 ns active high
framing pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS
operation at 8.192 Mb/s. See Figure 20.
Clock 1.544 MHz (CMOS Output).
This output is used in T1 applications.
Clock 3.088 MHz (CMOS Output).
This output is used in T1 applications.
Clock 2.048 MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048 Mb/s.
Description (see notes 1 to 5)
3
SEC
4
5,18
6
PRI
V
DD
OSCo
7
OSCi
8
F16o
9
F0o
10
F8o
11
12
13
C1.5o
C3o
C2o
Zarlink Semiconductor Inc.
C3o
C2o
C4o
VSS
C8o
C16o
VDD
PRI
SEC
3
MT9042C
Pin Description
Pin #
14
16
17
19
Name
C4o
C8o
C16o
GTi
Description (see notes 1 to 5)
Data Sheet
Clock 4.096 MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048 Mb/s
and 4.096 Mb/s.
Clock 8.192 MHz (CMOS Output).
This output is used for ST-BUS operation at 8.192 Mb/s.
Clock 16.384 MHz (CMOS Output).
This output is used for ST-BUS operation at
16.384 Mb/s.
Guard Time (Schmitt Input).
This input is used by the MT9042B state machine in both
Manual and Automatic modes. The signal at this pin affects the state changes between
Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and
Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o.
See Tables 4 and 5.
Guard Time (CMOS Output).
The LOS1 input is gated by the rising edge of F8o, buffered
and output on GTo. This pin is typically used to drive the GTi input through an RC circuit.
Secondary Reference Loss (TTL Input).
This input is normally connected to the loss of
signal (LOS) output signal of a Line Interface Unit (LIU). When high, the SEC reference signal
is lost or invalid. LOS2, along with the LOS1 and GTi inputs control the MT9042B state
machine when operating in Automatic Control. The logic level at this input is gated in by the
rising edge of F8o.
Primary Reference Loss (TTL Input).
Typically, external equipment applies a logic high to
this input when the PRI reference signal is lost or invalid. The logic level at this input is gated
in by the rising edge of F8o. See LOS2 description.
Mode/Control Select 2 (TTL Input).
This input, in conjunction with MS1, determines the
device’s mode (Automatic or Manual) and state (Normal, Holdover or Freerun) of operation.
The logic level at this input is gated in by the rising edge of F8o. See Table 3.
Mode/Control Select 1 (TTL Input).
The logic level at this input is gated in by the rising
edge of F8o. See pin description for MS1.
Reference Source Select (TTL Input).
In Manual Control, a logic low selects the PRI
(primary) reference source as the input reference signal and a logic high selects the SEC
(secondary) input. In Automatic Control, this pin must be at logic low. The logic level at this
input is gated in by the rising edge of F8o. See Table 2.
Frequency Select 2 (TTL Input).
This input, in conjunction with FS1, selects which of three
possible frequencies (8 kHz, 1.544 MHz, or 2.048 MHz) may be input to the PRI and SEC
inputs. See Table 1.
Frequency Select 1 (TTL Input).
See pin description for FS2.
Reset (Schmitt Input).
A logic low at this input resets the MT9042C. To ensure proper
operation, the device must be reset after changes to the method of control, reference signal
frequency changes and power-up. The RST pin should be held low for a minimum of 300 ns.
While the RST pin is low, all frame and all clock outputs except C16o are at logic high; C16o is
at logic low. Following a reset, the input reference source and output clocks and frame pulses
are phase aligned as shown in Figure 19.
20
21
GTo
LOS2
22
LOS1
23
MS2
24
25
MS1
RSEL
26
FS2
27
28
FS1
RST
Notes:
1. All inputs are CMOS with either TTL compatible logic levels, CMOS compatible logic levels or Schmitt trigger compatible logic levels
as indicated in the Pin Description.
2. All outputs are CMOS with CMOS compatible logic levels.
3. See DC Electrical Characteristics for static logic threshold values.
4. See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for dynamic logic threshold values.
5. Unless otherwise stated, all unused inputs should be connected to logic high or logic low and all unused outputs should be left open
circuit.
4
Zarlink Semiconductor Inc.
MT9042C
Functional Description
Data Sheet
The MT9042C is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links.
Figure 1 is a functional block diagram which is described in the following sections.
Reference Select MUX Circuit
The MT9042C accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables
1, 4 and 5.
Frequency Select MUX Circuit
The MT9042C operates with one of three possible input reference frequencies (8 kHz, 1.544 MHz or 2.048 MHz).
The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference
inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be
performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and
must not be used. See Table 1.
FS2
0
0
1
1
FS1
0
1
0
1
Input Frequency
Reserved
8kHz
1.544MHz
2.048MHz
Table 1 - Input Frequency Selection
Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or
SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.
During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary
reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL will
lead to unacceptable phase changes in the output signal.
As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the
signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is
input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.
During a switch, from one reference to the other, the State Machine first changes the mode of the device from
Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an
accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between
the current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to
the Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase
position as the previous reference signal would have been if the reference switch not taken place. The State
Machine then returns the device to Normal Mode.
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