ISO-CMOS
MT8816
8 x 16 Analog Switch Array
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
Internal control latches and address decoder
Short set-up and hold times
Wide operating voltage: 4.5 V to 13.2 V
12Vpp analog signal capability
R
ON
65
max. @ V
DD
= 12 V, 25C
R
ON
10
@ V
DD
= 12 V, 25C
Full CMOS switch for low distortion
Minimum feedthrough and crosstalk
Separate analog and digital reference supplies
Low power consumption ISO-CMOS technology
Ordering Information
MT8816AP1
MT8816APR1
MT8816AE1
MT8816AF1
44 Pin PLCC*
44 Pin PLCC*
40 Pin PDIP*
44 Pin TQFP*
* Pb Free Matte Tin
-40C to +85C
September 2011
Tubes
Tape & Reel
Tubes
Trays
Description
The Zarlink MT8816 is fabricated in Zarlink’s ISO-
CMOS technology providing low power dissipation and
high reliability. The device contains a 8 x 16 array of
crosspoint switches along with a 7 to 128 line decoder
and latch circuits. Any one of the 128 switches can be
addressed by selecting the appropriate seven address
bits. The selected switch can be turned on or off by
applying a logical one or zero to the DATA input. V
SS
is
the ground reference of the digital inputs. The range of
the analog signal is from V
DD
to V
EE
. Chip Select (CS)
allows the crosspoint array to be cascaded for matrix
expansion.
Applications
•
•
•
•
•
•
Key systems
PBX systems
Mobile radio
Test equipment/instrumentation
Analog/digital multiplexers
Audio/Video switching
CS
STROBE
DATA RESET
VDD
VEE
VSS
AX0
AX1
AX2
AX3
AY0
AY1
AY2
1
1
••••••••••••••••
7 to 128
Decoder
Latches
8 x 16
Switch
Array
128
Xi I/O
(i=0-15)
128
•••••••••••••••••••
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.
MT8816
Change Summary
Changes from the January 2010 issue to the September 2011 issue.
Data Sheet
Page
1
Item
Ordering Information
Change
Removed leaded packages as per PCN notice.
40 PIN PLASTIC DIP
44 43 42 4140 39 38 37 36 3534
NC
X14
X15
X6
X7
X8
X9
X10
X11
Y7
NC
1
2
3
4
5
6
7
8
9
10
11
12 13 14 1516 17 18 19 20 2122
VSS
Y6
STROBE
Y5
VEE
Y4
AX1
AX2
AY0
AY1
NC
33
32
31
30
29
28
27
26
25
24
23
NC
Y0
X0
X1
X2
X3
X4
X5
X12
X13
NC
Figure 2 - Pin Connections
2
Zarlink Semiconductor Inc.
RESET
NC
AY2
Y3
VDD
Y2
DATA
Y1
CS
AX0
AX3
44 PIN TQFP
VSS
Y6
STROBE
Y5
VEE
Y4
AX1
AX2
AY0
AY1
NC
44 PIN PLCC
Y3
AY2
RESET
AX3
AX0
X14
X15
X6
X7
X8
X9
X10
X11
NC
Y7
VSS
Y6
STROBE
Y5
VEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
Y2
DATA
Y1
CS
Y0
NC
X0
X1
X2
X3
X4
X5
X12
X13
AY1
AY0
AX2
AX1
Y4
X14
X15
X6
X7
X8
X9
X10
X11
NC
NC
Y7
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
NC
AX0
AX3
RESET
AY2
Y3
VDD
Y2
DATA
Y1
CS
Y0
NC
X0
X1
X2
X3
X4
X5
X12
X13
NC
MT8816
Pin Description
Pin #
Name
TQFP
PDIP
PLCC
Data Sheet
Description
Y3 Analog (Input/Output):
this is connected to the Y3 column of the
switch array.
Y2 Address Line (Input).
Master RESET (Input):
this is used to turn off all switches regardless
of the condition of CS. Active High.
39
40
42
43,44
2, 3
4-9
41,1,11
10
12
13
14
1
2
3
4,5
6,7
8-13
14
15
16
17
18
1
2
3
4,5
7,8
9-14
6,15,16
17
18
19
20
Y3
AY2
RESET
AX3,AX0
X3 and X0 Address Lines (Inputs).
X14, X15
X14 and X15 Analog (Inputs/Outputs):
these are connected to the
X14 and X15 rows of the switch array.
X6-X11
NC
Y7
V
SS
Y6
X6-X11 Analog (Inputs/Outputs):
these are connected to the X6-
X11 rows of the switch array.
No Connection
Y7 Analog (Input/Output):
this is connected to the Y7 column of the
switch array.
Digital Ground Reference.
Y6 Analog (Input/Output):
this is connected to the Y6 column of the
switch array.
STROBE
STROBE (Input):
enables function selected by address and data.
Address must be stable before STROBE goes high and DATA must
be stable on the falling edge of the STROBE. Active High.
Y5
V
EE
Y4
Y5 Analog (Input/Output):
this is connected to the Y5 column of the
switch array.
Negative Power Supply.
Y4 Analog (Input/Output):
this is connected to the Y4 column of the
switch array.
15
16
17
18,19
20,21
24,25
26-31
22,23,33
32
34
19
20
21
22, 23
24, 25
26, 27
28 - 33
34
35
36
21
22
23
24,25
26,27
30,31
32-37
28,29,
38
39
40
AX1,AX2
X1 and X2 Address Lines (Inputs).
AY0,AY1
Y0 and Y1 Address Lines (Inputs).
X13, X12
X13 and X12 Analog (Inputs/Outputs):
these are connected to the
X13 and X12 rows of the switch array.
X5-X0
NC
Y0
CS
X5-X0 Analog (Inputs/Outputs):
these are connected to the X5-X0
rows of the switch array.
No Connection.
Y0 Analog (Input/Output):
this is connected to the Y0 column of the
switch array.
Chip Select (Input):
this is used to select the device. Active High.
3
Zarlink Semiconductor Inc.
MT8816
Pin Description (continued)
Pin #
Name
TQFP
PDIP
PLCC
Data Sheet
Description
Y1 Analog (Input/Output):
this is connected to the Y1 column of the
switch array.
DATA (Input):
a logic high input will turn on the selected switch and a
logic low will turn off the selected switch. Active High.
Y2 Analog (Input/Output):
this is connected to the Y2 column of the
switch array.
Positive Power Supply.
35
36
37
38
37
38
39
40
41
42
43
44
Y1
DATA
Y2
V
DD
4
Zarlink Semiconductor Inc.
MT8816
Functional Description
Data Sheet
The MT8816 is an analog switch matrix with an array size of 8 x 16. The switch array is arranged such that there
are 8 columns by 16 rows. The columns are referred to as the Y inputs/outputs and the rows are the X
inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and
provide a high degree of isolation when turned off. The control memory consists of a 128 bit write only RAM in
which the bits are selected by the address inputs (AY0-AY2, AX0-AX3). Data is presented to the memory on the
DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs
are high and are latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the
corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches
corresponding to the addressed memory location are altered when data is written into memory. The remaining
switches retain their previous states. Any combination of X and Y inputs/outputs can be interconnected by
establishing appropriate patterns in the control memory. A logical “1” on the RESET input will asynchronously return
all memory locations to logical “0” turning off all crosspoint switches regardless of whether CS is high or low.
Two voltage reference pins (V
SS
and V
EE
) are provided for the MT8816 to enable switching of negative analog
signals. The range for digital signals is from V
DD
to V
SS
while the range for analog signals is from V
DD
to V
EE
. V
SS
and V
EE
pins can be tied together if a single voltage reference is needed.
Address Decode
The seven address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable
signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To
write to a location, RESET must be low and CS must go high while the address and data are set up. Then the
STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is
high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be
stable on the falling edge of STROBE in order for correct data to be written to the latch.
Applications
Figure 3 shows a typical Operating Circuit of a video surveillance system using analog crosspoint switches which
allow multiple video sources switched to multiple output devices, e.g., video monitor, video recorder etc.
Analog Crosspoint Switch
Quad Video Amplifiers
Quad Video Drivers
NTSC
/ PAL
Cameras
Video
Monitors
Figure 3 - Typical Video Surveillance System
5
Zarlink Semiconductor Inc.
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