IDT
TM
Interprise
TM
Integrated
Communications Processor
3.3V and 2.5V Devices
Device Overview
The RC32333 device is a member of the IDT™ Interprise™ family of
integrated communications processors. This product incorporates a
high-performance, low-cost 32-bit CPU core with functionality common
to a large number of embedded applications. The RC32333 integrates
these functions to enable the use of low-cost PC commodity market
memory and I/O devices, allowing the aggressive price/performance
characteristics of the CPU to be realized quickly into low-cost systems.
The RC32333 device is available with either a 3.3V or 2.5V operating
voltage. Differences between the two versions are noted where appli-
cable.
79RC32333
Features
◆
RC32300 32-bit Microprocessor
– Up to 150 MHz operation
– Enhanced MIPS-II Instruction Set Architecture (ISA)
– Cache prefetch instruction
– Conditional move instruction
– DSP instructions
– Supports big or little endian operation
– MMU with 32 page TLB
– 8KB Instruction Cache, 2-way set associative
– 2KB Data Cache, 2-way set associative
– Cache locking per line
– Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
– Compatible with a wide variety of operating systems
◆
Local Bus Interface
– Up to 75 MHz operation
– 23-bit address bus
– 32-bit data bus
– Direct control of local memory and peripherals
– Programmable system watch-dog timers
– Big or little endian support
◆
Interrupt Controller simplifies exception management
◆
Four general purpose 32-bit timer/counters
◆
Programmable I/O (PIO)
– Input/Output/Interrupt source
– Individually programmable
◆
SDRAM Controller (32-bit memory only)
– 4 banks, non-interleaved
– Up to 512MB total SDRAM memory supported
– Implements full, direct control of discrete, SODIMM, or DIMM
memories
– Supports 16Mb through 512Mb SDRAM device depths
– Automatic refresh generation
Block Diagram
EJTAG
In-Circuit Emulator Interface
RISCore 32300
Enhanced MIPS-II ISA
Integer CPU
RC5000
Compatible
CP0
32-page
TLB
Interrupt Control
Programmable I/O
32-bit Timers
SPI Control
DMA Control
Local
Memory/IO
Control
UART
IPBus
Bridge
2KB
2-set, Lockable
Data Cache
8KB
2-set
Lockable
Instr. Cache
IDT
Peripheral
Bus
SDRAM
Control
PCI Bridge
Figure 1 RC32333 Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 30
©
2004 Integrated Device Technology, Inc.
May 4, 2004
DSC 6402
IDT 79RC32333
Serial Peripheral Interface (SPI) master mode interface
◆
UART Interface
– 16550 compatible UART
– Baud rate support up to 1.5 Mb/s
◆
Memory & Peripheral Controller
– 6 banks, up to 8MB per bank
– Supports 8-,16-, and 32-bit interfaces
– Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation
– 8-bit boot PROM support
– Flexible I/O timing protocols
◆
4 DMA Channels
– 4 general purpose DMA, each with endianess swappers and
byte lane data alignment
– Supports scatter/gather, chaining via linked lists of records
– Supports memory-to-memory, memory-to-I/O, memory-to-
PCI, PCI-to-PCI, and I/O-to-I/O transfers
– Supports unaligned transfers
– Supports burst transfers
– Programmable DMA bus transactions burst size
(up to 16 bytes)
◆
PCI Bus Interface
– 32-bit PCI, up to 50 MHz
– Revision 2.2 compatible
– Target or master
– Host or satellite
– Three slot PCI arbiter
– Serial EEPROM support, for loading configuration registers
◆
Off-the-shelf development tools
◆
JTAG Interface (IEEE Std. 1149.1 compatible)
◆
208 QFP Package
◆
3.3V or 2.5V core supply with 3.3V I/O supply
– 3.3V core supply is 5V I/O tolerant
◆
EJTAG in-circuit emulator interface
◆
CPU Execution Core
The RC32333 integrates the RISCore 32300, the same CPU core
found in the award-winning RC32364 microprocessor. The RISCore
32300 implements the Enhanced MIPS-II ISA. Thus, it is upwardly
compatible with applications written for a wide variety of MIPS architec-
ture processors, and it is kernel compatible with the modern operating
systems that support IDT’s 64-bit RISController product family. The
RISCore 32300 was explicitly defined and designed for integrated
processor products such as the RC32333. Key attributes of the execu-
tion core found within this product include:
◆
High-speed, 5-stage scalar pipeline executes to 150MHz. This
high performance enables the RC32333 to perform a variety of
performance intensive tasks, such as routing, DSP algorithms,
etc.
◆
32-bit architecture with enhancements of key capabilities. Thus,
the RC32333 can execute existing 32-bit programs, while
enabling designers to take advantage of recent advances in
CPU architecture.
◆
Count leading-zeroes/ones. These instructions are common to a
wide variety of tasks, including modem emulation, voice over IP
compression and decompression, etc.
◆
Cache PREFetch instruction support, including a specialized
form intended to help memory coherency. System programmers
can allocate and stage the use of memory bandwidth to achieve
maximum performance.
◆
8KB of 2-way set associative instruction cache
Serial
Channel
Programmable I/O
Serial
EEPROM
RC32333
SDRAM
Local
Memory
I/O Bus
FLASH
Local I/O
32-bit, 50MHz PCI
Figure 2 RC32333 Based System Diagram
2 of 30
May 4, 2004
IDT 79RC32333
◆
◆
◆
◆
2KB of 2-way set associative data cache, capable of write-back
and write-through operation.
Cache locking per line to speed real-time systems and critical
system functions
On-chip TLB to enable multi-tasking in modern operating
systems
EJTAG interface to enable sophisticated low-cost in-circuit
emulation.
PCI Bus Bridge
In order to leverage the wide availability of low-cost peripherals for
the PC market as well as to simplify the design of add-in functions, the
RC32333 integrates a full 32-bit PCI bus bridge. Key attributes of this
bridge include:
◆
50 MHz operation
◆
PCI revision 2.2 compliant
◆
Programmable address mappings between CPU/Local memory
and PCI memory and I/O
◆
On-chip PCI arbiter
◆
Extensive buffering allows PCI to operate concurrently with local
memory transfers
◆
Selectable byte-ordering swapper.
Synchronous-DRAM Interface
The RC32333 integrates a SDRAM controller which provides direct
control of system SyncDRAM running at speeds to 75MHz.
Key capabilities of the SDRAM controller include:
◆
Direct control of 4 banks of SDRAM (up to 2 64-bit wide DIMMs)
◆
On-chip page comparators optimize access latency.
◆
Speeds to 75MHz
◆
Programmable address map.
◆
Supports 16, 64, 128, 256, or 512Mb SDRAM devices
◆
Automatic refresh generation driven by on-chip timer
◆
Support for discrete devices, SODIMM, or DIMM modules.
Thus, systems can take advantage of the full range of commodity
memory that is available, enabling system optimization for cost, real-
estate, or other attributes.
On-Chip DMA Controller
To minimize CPU exception handling and maximize the efficiency of
system bandwidth, the RC32333 integrates a very sophisticated
4-channel DMA controller on chip.
The RC32333 DMA controller is capable of:
◆
Chaining and scatter/gather support through the use of a
flexible, linked list of DMA transaction descriptors
◆
Capable of memory<->memory, memory<->I/O, and
PCI<->memory DMA
◆
Unaligned transfer support
◆
Byte, halfword, word, quadword DMA support.
Local Memory and I/O Controller
The local memory and I/O controller implements direct control of
external memory devices, including the boot ROM as well as other
memory areas, and also implements direct control of external periph-
erals.
The local memory controller is highly flexible, allowing a wide range
of devices to be directly controlled by the RC32333 processor. For
example, a system can be built using an 8-bit boot ROM, 16-bit FLASH
cards (possibly on PCMCIA), a 32-bit SRAM or dual-port memory, and a
variety of low-cost peripherals.
Key capabilities include:
◆
Direct control of EPROM, FLASH, RAM, and dual-port memories
◆
6 chip-select outputs, supporting up to 8MB per memory space
◆
Supports mixture of 8-, 16-, and 32-bit wide memory regions
◆
Flexible timing protocols allow direct control of a wide variety of
devices
◆
Programmable address map for 2 chip selects
◆
Automatic wait state generation.
On-Chip Peripherals
The RC32333 also integrates peripherals that are common to a wide
variety of embedded systems.
◆
Single 16550 compatible UART.
◆
SPI master mode interface for direct interface to EEPROM,
A/D, etc.
◆
Interrupt Controller to speed interrupt decode and management
◆
Four 32-bit on-chip Timer/Counters
◆
Programmable I/O module
Debug Support
To facilitate rapid time to market, the RC32333 provides extensive
support for system debug.
First and foremost, this product integrates an EJTAG in-circuit
emulation module, allowing a low-cost emulator to interoperate with
programs executing on the controller. By using an augmented JTAG
interface, the RC32333 is able to reuse the same low-cost emulators
developed around the RC32364 CPU.
3 of 30
May 4, 2004
IDT 79RC32333
Secondly, the RC32333 implements additional reporting signals
intended to simplify the task of system debugging when using a logic
analyzer. This product allows the logic analyzer to differentiate transac-
tions initiated by DMA from those initiated by the CPU and further allows
CPU transactions to be sorted into instruction fetches vs. data fetches.
Finally, the RC32333 implements a full boundary scan capability,
allowing board manufacturing diagnostics and debug.
Packaging
The RC32333 is packaged using a 208 Quad Flat Pack (QFP)
package.
Thermal Considerations
The RC32333 consumes less than 2.0 W peak power. The device is
guaranteed in an ambient temperature range of 0° to +70° C for
commercial temperature devices; -40° to +85° C for industrial tempera-
ture devices.
Revision History
March 5, 2003:
Initial publication of 2.5V Revision X silicon.
September 2, 2003:
Added 2.5V version of device. Changed tables
to include 2.5V values where appropriate. Added a Power Consumption
table, Temperature and Voltage table, and Power Curves for the 2.5V
device. In the PCI category of Table 6, created separate sections for
3.3V and 2.5V devices and in 2.5V section changed time to 4 ns for
pci_cbe_n[3:0], pci_frame_n, pci_trdy_n, and pci_irdy_n. In Table 8,
added 3 new categories (Input Pads, PCI Input Pads, and All Pads) and
added footnotes 2 and 3. In Table 13, pins 181 and 184 were changed
from Vcc Core to Vcc I/O.
March 24, 2004:
In Table 1, changed description in Satellite Mode
for pci_rst_n. Specified “cold” reset on pages 12 and 13. Changed
several values in Table 12, Absolute Maximum Ratings, and changed
footnote 1 to that table.
May 4, 2004:
Revised values in Table 11, Power Consumption —
2.5V Device.
4 of 30
May 4, 2004
IDT 79RC32333
Pin Description Table
The following table lists the pins provided on the RC32333. Note that those pin names followed by “_n” are active-low signals. All external pull-ups
and pull-downs require
10 kΩ resistor.
Name
Type
Reset
Drive
State
Strength
Status Capability
Description
Local System Interface
mem_data[31:0]
mem_addr[22:2]
I/O
I/O
Z
[22:10] Z
[9:2] L
High
Local system data bus
Primary data bus for memory. I/O and SDRAM.
[22:17] Low
Memory Address Bus
These signals provide the Memory or DRAM address, during a Memory or DRAM bus transaction. During
[16:2] High each word data, the address increments either in linear or sub-block ordering, depending on the transac-
tion type. The table below indicates how the memory write enable signals are used to address discreet
memory port width types.
Port Width
32-bit
16-bit
8-bit
Pin Signals
mem_we_n[3]
mem_we_n[3]
mem_we_n[2] mem_we_n[1]
mem_we_n[2]
mem_we_n[2]
mem_we_n[1]
mem_we_n[1]
Not Used (Driven
Low)
mem_addr[0]
mem_we_n[0]
mem_we_n[0]
mem_we_n[0]
Byte Low Write
Enable
Byte Write Enable
DMA (32-bit) mem_we_n[3]
Byte High Write Enable mem_addr[1]
Not Used (Driven High) mem_addr[1]
mem_addr[22] Alternate function: reset_boot_mode[1].
mem_addr[21] Alternate function: reset_boot_mode[0].
mem_addr[20] Alternate function: reset_pci_host_mode.
mem_addr[19] Alternate function: modebit [9].
mem_addr[18] Alternate function: modebit [8].
mem_addr[17] Alternate function: modebit [7].
mem_addr[16] Alternate function: sdram_addr[16].
mem_addr[15] Alternate function: sdram_addr[15].
mem_addr[14] Alternate function: sdram_addr[14].
mem_addr[13] Alternate function: sdram_addr[13].
mem_addr[11] Alternate function: sdram_addr[11].
mem_addr[10] Alternate function: sdram_addr[10].
mem_addr[9] Alternate function: sdram_addr[9].
mem_addr[8] Alternate function: sdram_addr[8].
mem_addr[7] Alternate function: sdram_addr[7].
mem_addr[6] Alternate function: sdram_addr[6].
mem_addr[5] Alternate function: sdram_addr[5].
mem_addr[4] Alternate function: sdram_addr[4].
mem_addr[3] Alternate function: sdram_addr[3].
mem_addr[2] Alternate function: sdram_addr[2].
mem_cs_n[5:0]
mem_oe_n
mem_we_n[3:0]
Output
Output
Output
H
H
H
Low
High
High
Memory Chip Select Negated
Recommend an external pull-up.
Signals that a Memory Bank is actively selected.
Memory Output Enable Negated
Recommend an external pull-up.
Signals that a Memory Bank can output its data lines onto the cpu_ad bus.
Memory Write Enable Negated Bus
Signals which bytes are to be written during a memory transaction. Bits act as Byte Enable and
mem_addr[1:0] signals for 8-bit or 16-bit wide addressing.
Table 1 Pin Descriptions (Part 1 of 6)
5 of 30
May 4, 2004
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
