Si5350C
F
ACTORY
- P
ROGRAMMABLE
A
NY
- F
REQUENCY
CMOS
C
L O C K
G
ENERATOR
+ PLL
Features
Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
Exact frequency synthesis at each
output (0 ppm error)
Glitchless frequency changes
Low output period jitter: 100 ps pp
Configurable Spread Spectrum
selectable at each output
User-configurable control pins:
Output Enable (OEB_0/1/2)
Power Down (PDN)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)
Loss of Lock Status (LOL)
Supports static phase offset
Rise/fall time control
Operates from a low-cost, fixed
frequency crystal: 25 or 27 MHz
Separate voltage supply pins:
Core VDD: 2.5 V or 3.3 V
Output VDDO: 2.5 V or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
(<45 mA)
Available in 3 packages types:
10-MSOP: 3 outputs
24-QSOP: 8 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
10-MSOP
24-QSOP
Applications
20-QFN
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
The Si5350C generates free-running and/or synchronized clocks selectable on each
of its outputs. A dual PLL + high resolution MultiSynth
TM
fractional divider
architecture enables this user-definable custom timing device to generate any of the
specified output frequencies at any of its outputs. This allows the Si5350C to replace
a combination of crystals, crystal oscillators, and synchronized clocks (PLL). Custom
pin-controlled Si5350C devices are requested using the ClockBuilder web-based
part number utility (www.silabs.com/ClockBuilder).
Ordering Information:
See Page 18
20-QFN, 24-QSOP
10-MSOP
XA
OSC
PLLA
Multi
Synth
0
Multi
Synth
1
PLLB
Multi
Synth
2
XA
OSC
PLLA
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
PLLB
Multi
Synth
3
Multi
Synth
4
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK0
CLK1
CLK2
XB
XB
CLKIN
CLKIN
Control
Logic
P0
P0
Si5350C
P1
P2
P3
Multi
Synth
5
Control
Logic
Multi
Synth
6
Multi
Synth
7
Si5350C
Rev. 0.9 5/11
Copyright © 2011 by Silicon Laboratories
Si5350C
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5350C
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si5350C Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Replacing a Crystal with a Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Configuring the Si5350C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. External Clock Input Pin (CLKIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4. Programmable Control Pins (P0–P3) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Pin Descriptions (20-QFN, 24-QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. Pin Descriptions (10-MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. Package Outline (24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9. Package Outline (20-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10. Package Outline (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Rev. 0.9
3
Si5350C
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
Ambient Temperature
Core Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
3.0
2.25
3.0
Typ
25
3.3
2.5
3.3
2.5
Max
85
3.0
2.75
3.60
2.75
Unit
°C
V
V
V
V
Output Buffer Voltage
V
DDOx
2.25
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Symbol
Test Condition
Enabled 3 outputs
Min
—
—
—
—
—
—
—
Typ
20
25
—
2.0
Max
35
45
20
4.5
Unit
mA
mA
µA
mA
µA
µA
Core Supply Current*
I
DD
Enabled 8 outputs
Power Down (PDN = V
DD
)
Output Buffer Supply
Current (Per Output)*
I
DDOx
I
P1-P3
I
P0
C
L
= 5 pF
Pins P1, P2, P3
Vin < 3.6 V
Pin P0
8 mA output drive current, see
Design Considerations section
—
—
85
10
30
—
Input Current
Output Impedance
Z
OI
*Note:
Output clocks less than or equal to 133 MHz.
4
Rev. 0.9
Si5350C
Table 3. AC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
Power-Up Time
Power-Down Time
Output Enable Time
Output Frequency Transition
Time
Spread Spectrum Frequency
Deviation
Spread Spectrum
Modulation Rate
Symbol
T
RDY
T
PD
T
OE
T
FREQ
SS
DEV
SS
MOD_C
Test Condition
From V
DD
= V
DDmin
to valid
output clock, C
L
= 5 pF,
f
CLKn
> 1 MHz
From V
DD
= V
DDmin
, C
L
= 5 pF,
f
CLKn
> 1 MHz
From OEB assertion to valid
clock output, C
L
= 5 pF, f
CLKn
> 1 MHz
f
CLKn
> 1 MHz
Down Spread
Min
—
—
—
—
–0.5
30
Typ
2
5
—
—
—
31.5
Max
10
100
10
10
–2.5
33
Unit
ms
ms
µs
µs
%
kHz
Table 4. Input Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Crystal Frequency
P0-P3 Input Low Voltage
P0-P3 Input High Voltage
CLKIN Frequency Range
CLKIN Input Low Voltage
CLKIN Input High Voltage
Symbol
f
XTAL
V
IL_P0-3
V
IH_P0-3
f
CLKIN
V
IL_CLKIN
V
IH_CLKIN
Test Condition
Min
25
–0.1
0.7 x V
DD
10
–0.1
0.7 x V
DD
Typ
—
—
—
—
—
—
Max
27
0.3 x V
DD
3.60
100
0.3 x V
DD
3.60
Units
MHz
V
V
MHz
V
V
Table 5. Output Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Frequency Range
Load Capacitance
Duty Cycle
Rise/Fall Time
Output High Voltage
Output Low Voltage
Period Jitter
Cycle-to-Cycle Jitter
RMS Phase Jitter
Symbol
F
CLK
C
L
DC
t
r
/t
f
V
OH
V
OL
J
PER
J
CC
J
RMS
Test Condition
Min
0.008
Typ
—
—
50
1
—
—
60
50
5
Max
160
15
55
1.5
—
0.6
100
95
10
Units
MHz
pF
%
ns
F
CLK
< 100 MHz
Measured at V
DD
/2
20%–80%, C
L
= 5 pF
C
L
= 5 pF
Measured over 10k cycles
Measured over 10k cycles
12 kHz–20 MHz
—
45
0.5
V
DD
– 0.6
—
—
—
—
V
V
ps pk-pk
ps pk
ps
Rev. 0.9
5
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