Si5350B
F
ACTORY
- P
ROGRAMMABLE
A
NY
- F
REQUENCY
CMOS
C
L O C K
G
ENERATOR
+ V C X O
Features
Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
Exact frequency synthesis at each
output (0 ppm error)
Highly linear VCXO gain (kv)
Glitchless frequency changes
Configurable Spread Spectrum
selectable at each output
User-configurable control pins:
Output Enable (OEB_0/1/2)
Power Down (PDN)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)
Supports static phase offset
Rise/fall time control
Operates from a low-cost, fixed
frequency AT-cut, non-pullable
crystal: 25 or 27 MHz
Separate voltage supply pins:
Core VDD: 2.5 V or 3.3 V
Output VDDO: 2.5 V or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Low output period jitter: 100 ps pp
Very low power consumption
(<40 mA)
Available in 3 packages types:
10-MSOP: 3 outputs
24-QSOP: 8 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
10-MSOP
24-QSOP
20-QFN
Applications
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Residential gateways
Networking/communication
Servers, storage
XO replacement
Ordering Information:
See page 19
Description
The Si5350B combines a clock generator and VCXO function into a single device. A
flexible architecture enables this user definable custom timing device to generate
any of the specified output frequencies from either the internal PLL or the VCXO.
This allows the Si5350B to replace multiple crystals, crystal oscillators, and VCXOs.
Custom pin-controlled Si5350B devices are requested using the ClockBuilder web-
based utility (www.silabs.com/ClockBuilder).
Functional Block Diagram
20-QFN, 24-QSOP
10-MSOP
XA
OSC
PLL
Multi
Synth
0
Multi
Synth
1
VCXO
Multi
Synth
2
Multi
Synth
0
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
XA
OSC
PLL
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
CLK0
CLK1
CLK2
XB
XB
Vc
VCXO
Vc
P0
Control
Logic
P0
Si5350B
P1
P2
P3
Multi
Synth
5
Control
Logic
Multi
Synth
6
Multi
Synth
7
Si5350B
Rev. 0.9 5/11
Copyright © 2011 by Silicon Laboratories
Si5350B
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5350B
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si5350B Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Replacing a Crystal with a Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Configuring the Si5350B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. Programmable Control Pins (P0–P3) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4. Voltage Control Input (VC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Pin Descriptions (20-QFN, 24-QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6. Pin Descriptions (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Package Outline (24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9. Package Outline (20-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10. Package Outline (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Rev. 0.9
3
Si5350B
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
Ambient Temperature
Core Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
3.0
2.25
2.25
Typ
25
3.3
2.5
2.5
3.3
Max
85
3.60
2.75
2.75
3.60
Unit
°C
V
V
V
V
Output Buffer Voltage
V
DDOx
3.0
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
Symbol
Test Condition
Enabled 3 outputs
Min
—
—
—
—
—
—
—
Typ
20
25
—
2.0
—
—
85
Max
30
40
15
4.5
10
30
—
Unit
mA
mA
µA
mA
µA
µA
Core Supply Current*
I
DD
Enabled 8 outputs
Power Down (PDN = V
DD
)
Output Buffer Supply Current
(Per Output)*
Input Current
I
DDOx
I
P0-P3
I
VC
C
L
= 5 pF
Pins P0, P1, P2, P3
Vin < 3.6 V
VC
8 mA output drive current,
see Design Considerations
section
Output Impedance
Z
OI
*Note:
Output clocks less than or equal to 133 MHz.
4
Rev. 0.9
Si5350B
Table 3. AC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
VCXO Control Voltage Range
VCXO Gain (configurable)
VCXO Control Voltage Linearity
VCXO Pull Range
(configurable)*
VCXO Modulation Bandwidth
Power-Up Time
Symbol
Vc
kv
KVL
PR
Test Condition
Min
0
Typ
V
DD
/2
—
—
0
10
2
Max
V
DD
150
+5
±240
—
10
Unit
V
ppm/V
%
ppm
kHz
ms
Vc = 10–90% of V
DD
Vc = 10–90% of V
DD
V
DD
= 3.3 V
Vc = 10–90% of V
DD
18
–5
±30
—
TRDY
From V
DD
= V
DDmin
to valid
output clock, C
L
= 5 pF,
f
CLKn
> 1 MHz
From V
DD
= V
DDmin
,
C
L
= 5 pF, f
CLKn
> 1 MHz
From OEB assertion to valid
clock output, C
L
= 5 pF,
f
CLKn
> 1 MHz
f
CLKn
> 1 MHz
Down spread
—
Power-Down Time
T
PD
—
5
100
ms
Output Enable Time
Output Frequency Transition
Time
Spread Spectrum Frequency
Deviation
Spread Spectrum Modulation
Rate
T
OE
—
—
10
µs
T
FREQ
SS
DEV
SS
MOD
—
–0.5
30
—
—
31.5
10
–2.5
33
µs
%
kHz
*Note:
Contact Silicon Labs for VCXO operation at 2.5 V.
Table 4. Input Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
VC Input Resistance
P0-P3 Input Low Voltage
P0-P3 Input High Voltage
Symbol
Test Condition
Min
100
Typ
—
—
—
Max
—
0.3 x V
DD
3.60
Units
k
V
V
VIL-P0-3
VIH_P0-3
–0.1
0.7 x V
DD
Rev. 0.9
5
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