ADC0801S040
Single 8 bits ADC, up to 40 MHz
Rev. 03 — 2 July 2012
Product data sheet
1. General description
The ADC0801S040 is an 8-bit universal analog-to-digital converter (ADC) for video and
general purpose applications. It converts the analog input signal from 2.7 V to 5.5 V into
8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs
and outputs are CMOS/Transistor-Transistor Logic (TTL) compatible. A sleep mode
allows reduction of the device power consumption to 4 mW.
2. Features
8-bit resolution
Operation between 2.7 V and 5.5 V
Sampling rate up to 40 MHz
DC sampling allowed
High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits
at 4.43 MHz full-scale input at f
clk
= 40 MHz)
CMOS/TTL compatible digital inputs and outputs
External reference voltage regulator
Power dissipation only 30 mW (typical value)
Low analog input capacitance, no buffer amplifier required
Sleep mode (4 mW)
No sample-and-hold circuit required
3. Applications
Video data digitizing
Camera
Camcorder
Radio communication
Car alarm system
®
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
4. Quick reference data
Table 1.
Quick reference data
V
DDA
= V5 to V6 = 3.3 V; V
DDD
= V3 to V4 = 3.3 V; V
DDO
= V20 to V11 = 3.3 V; V
SSA
, V
SSD
and V
SSO
shorted together; V
i(a)(p-p)
= 1.84 V; C
L
= 20 pF; T
amb
= 0
C to 70
C; typical values measured at
T
amb
= 25
C unless otherwise specified.
Symbol
V
DDA
V
DDD
V
DDO
V
DD
I
DDA
I
DDD
I
DDO
INL
DNL
f
clk(max)
Parameter
analog supply
voltage
digital supply
voltage
output supply
voltage
supply voltage V
DDA
V
DDD
difference
V
DDD
V
DDO
analog supply
current
digital supply
current
output supply
current
integral
non-linearity
differential
non-linearity
maximum
clock
frequency
total power
dissipation
V
DDA
= V
DDD
= V
DDO
= 3.3 V
f
clk
= 40 MHz; ramp input;
C
L
= 20 pF
ramp input; see Figure 6
ramp input; see Figure 7
Conditions
Min
2.7
2.7
2.5
0.2
0.2
-
-
-
-
-
40
Typ
3.3
3.3
3.3
-
-
4
5
1
0.5
0.25
-
Max
5.5
5.5
5.5
+0.2
+2.25
6
8
2
0.75
0.5
-
Unit
V
V
V
V
V
mA
mA
mA
LSB
LSB
MHz
P
tot
-
30
53
mW
5. Ordering information
Table 2.
Ordering information
Package
Name
ADC0801S040TS
SSOP20
Description
plastic shrink small outline package; 20 leads; body width 4.4 mm
Version
SOT266-1
Type number
3ADC0801S040_3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
2 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
6. Block diagram
V
DDA
5
CLK
1
V
DDD
3
CLOCK DRIVER
RT
10
2
SLEEP
ADC0801S040
19 D7
MSB
18 D6
17 D5
R
lad
16 D4
analog
voltage input
VI
9
ANALOG - TO - DIGITAL
CONVERTER
LATCHES
CMOS
OUTPUTS
15 D3
14 D2
13 D1
12 D0
20
LSB
data outputs
RM
8
RB
7
V
DDO
6
V
SSA
analog ground
11
V
SSO
output ground
4
V
SSD
digital ground
014aaa495
Fig 1. Block diagram
3ADC0801S040_3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
3 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
7. Pinning information
7.1 Pinning
CLK
SLEEP
V
DDD
V
SSD
V
DDA
V
SSA
RB
RM
VI
1
2
3
4
5
6
7
8
9
20 V
DDO
19 D7
18 D6
17 D5
16 D4
ADC0801S
15 D3
040TS
14 D2
13 D1
12 D0
11 V
SSO
014aaa494
RT 10
Fig 2. Pin configuration
7.2 Pin description
Table 3.
Symbol
CLK
SLEEP
V
DDD
V
SSD
V
DDA
V
SSA
RB
RM
VI
RT
V
SSO
D0
D1
D2
D3
D4
D5
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Description
clock input
sleep mode input
digital supply voltage (2.7 V to 5.5 V)
digital ground
analog supply voltage (2.7 V to 5.5 V)
analog ground
reference voltage BOTTOM input
reference voltage MIDDLE
analog input voltage
reference voltage TOP input
output stage ground
data output; bit 0 (Least Significant Bit (LSB))
data output; bit 1
data output; bit 2
data output; bit 3
data output; bit 4
data output; bit 5
3ADC0801S040_3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
4 of 18
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
Table 3.
Symbol
D6
D7
V
DDO
Pin description
…continued
Pin
18
19
20
Description
data output; bit 6
data output; bit 7 (Most Significant Bit (MSB))
positive supply voltage for output stage (2.7 V to 5.5 V)
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DDA
V
DDD
V
DDO
V
DD
Parameter
analog supply voltage
digital supply voltage
output supply voltage
supply voltage difference
V
DDA
V
DDD
;
V
DDD
V
DDO
;
V
DDA
V
DDO
referenced to
V
SSA
Conditions
[1]
[1]
[1]
Min
0.3
0.3
0.3
0.1
Max
+7.0
+7.0
+7.0
+4.0
Unit
V
V
V
V
V
I
V
i(clk)(p-p)
I
O
T
stg
T
amb
T
j
[1]
input voltage
0.3
-
-
55
20
-
+7.0
V
DDD
10
+150
+75
150
V
V
mA
C
C
C
peak-to-peak clock input voltage referenced to
V
SSD
output current
storage temperature
ambient temperature
junction temperature
The supply voltages V
DDA
, V
DDD
and V
DDO
may have any value between
0.3
V and +7.0 V provided that
the supply voltage
V
DD
remains as indicated.
9. Thermal characteristics
Table 5.
Symbol
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction to
ambient
Condition
in free air
Value
120
Unit
K/W
10. Characteristics
Table 6.
Characteristics
V
DDA
= V5 to V6 = 3.3 V; V
DDD
= V3 to V4 = 3.3 V; V
DDO
= V20 to V11 = 3.3 V; V
SSA
, V
SSD
and V
SSO
shorted together; V
i(a)(p-p)
= 1.84 V; C
L
= 20 pF; T
amb
= 0
C to 70
C; typical values measured at T
amb
= 25
C unless otherwise specified.
Symbol
Supplies
V
DDA
V
DDD
V
DDO
3ADC0801S040_3
Parameter
analog supply voltage
digital supply voltage
output supply voltage
Conditions
Min
2.7
2.7
2.5
Typ
3.3
3.3
3.3
Max
5.5
5.5
5.5
Unit
V
V
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
5 of 18
实时操作系统RTOS
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