Another feature of the device is the ability to select
different bandwidth modes during normal operation
to allow for additional clock jitter attenuation.
Features
•
•
•
•
•
•
•
•
•
•
Four LVDS differential output pairs, and
one feedback output pair
One differential clock input pair PCLK, nPCLK can accept the
following differential input levels: LVDS, LVPECL, CML, SSTL
Maximum output frequency: 333.33MHz
VCO range: 1.2GHz – 2GHz
Cycle-to-cycle jitter: TBD
3.3V operating supply voltage
Two bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
External feedback for “zero delay” clock regeneration
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
The output frequency range is specified to include the most
common video rates used in professional video systems. With a
wide frequency range, the ICS864S004I is ideal for use in video
applications where zero-delay, low skew and jitter attenuation are
critical factors.
Pin Assignment
PLL_BYPASS
F_SEL2
F_SEL1
F_SEL0
GND
32 31 30 29 28 27 26 25
BW_SEL
V
DDA
V
DD
nc
PCLK
nPCLK
SE_CLK
nc
1
2
3
4
5
6
7
8
9
GND
V
DD
MR
nc
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
FB_OUT
CLK_SEL
nFB_IN
FB_IN
nFB_OUT
GND
V
DD
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
LVDS ZERO DELAY BUFFER
1
ICS864S004AKI REV. A OCTOBER 10, 2007
ICS864S004I
LVPECL ZERO DELAY BUFFER
PRELIMINARY
Block Diagram
50kHz or 1MHz
BW_SEL
Pulldown
Q0
CLK_SEL
Pullup
nQ0
Q1
PCLK
Pulldown
nPCLK
Pullup/Pulldown
1
1
Output
Divider
nQ1
Q2
nQ2
Phase
Detector
SE_CLK
Pulldown
0
VCO
(center @1.728GHZ)
0
Q3
nQ3
FB_IN
Pulldown
nFB_IN
Pullup/Pulldown
F_SEL[0:2]
Pulldown
3
FB_OUT
nFB_OUT
PLL_BYPASS
Pulldown
MR
Pulldown
IDT™ / ICS™
LVPECL ZERO DELAY BUFFER
2
ICS864S004AKI REV. A OCTOBER 10, 2007
ICS864S004I
LVPECL ZERO DELAY BUFFER
PRELIMINARY
Table 1. Pin Descriptions
Number
1
2
3, 16, 25
4, 8, 27
5
6
7
9, 15, 26
10
Name
BW_SEL
V
DDA
V
DD
nc
PCLK
nPCLK
SE_CLK
GND
CLK_SEL
Input
Power
Power
Unused
Input
Input
Input
Power
Input
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Type
Pulldown
Description
Selects between 50kHz and 1MHz PLL bandwidth modes. When HIGH
selects 1MHz PLL bandwidth. When LOW selects 50kHz PLL bandwidth.
嵌入式系统
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