August 1998
NDT3055L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance and provide superior
switching performance, and withstand high energy pulse
in the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such as
DC motor control and DC/DC conversion where fast
switching, low in-line power loss, and resistance to
transients are needed.
Features
4 A, 60 V. R
DS(ON)
= 0.100
Ω
@ V
GS
= 10 V,
R
DS(ON)
= 0.120
Ω
@ V
GS
= 4.5 V.
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH)
< 2V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
SuperSOT
TM
-3
SuperSOT -6
TM
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
D
D
D
D
S
D
SOT-223
S
G
D
S
G
SOT-223
*
(J23Z)
G
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
T
A
= 25
o
C unless otherwise noted
NDT3055L
60
±20
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
4
25
3
1.3
1.1
-65 to 150
W
T
J
,T
STG
R
θ
JA
R
θ
JC
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
42
12
°C/W
°C/W
* Order option J23Z for cropped center drain lead.
© 1998 Fairchild Semiconductor Corporation
NDT3055L Rev.A1
Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
I
D
= 250 µA, Referenced to 25
o
C
V
DS
= 60 V, V
GS
= 0 V
T
J
=125°C
I
GSSF
I
GSSR
V
GS(th)
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
(Note 2)
60
55
1
50
100
-100
V
mV/
o
C
µA
µA
nA
nA
∆
BV
DSS
/
∆
T
J
I
DSS
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
I
D
= 250 µA, Referenced to 25 C
V
GS
= 10 V, I
D
= 4 A
T
J
=125°C
V
GS
= 4.5 V, I
D
= 3.7 A
o
ON CHARACTERISTICS
Gate Threshold Voltage
Gate Threshold Voltage Temp. Coefficient
Static Drain-Source On-Resistance
1
1.6
-4
0.07
0.125
0.103
2
V
mV /
o
C
∆
V
GS(th)
/
∆
T
J
R
DS(ON)
0.1
0.18
0.12
Ω
I
D(ON)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
Notes:
On-State Drain Current
Forward Transconductance
V
GS
= 5 , V
DS
= 10 V
V
DS
= 5 V, I
D
= 4 A
V
DS
= 25, V
GS
= 0 V,
f = 1.0 MHz
10
7
A
S
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
345
110
30
pF
pF
pF
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 40 V, I
D
= 4 A,
V
GS
= 10 V
V
DD
= 25, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6
Ω
5
7.5
20
7
13
1.7
3.2
20
20
50
20
20
ns
ns
ns
ns
nC
nC
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 2.5 A
(Note 2)
2.5
0.8
1.2
A
V
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
guaranteed by design while R
θ
CA
is determined by the user's board design.
the drain pins. R
θ
JC
is
a. 42
o
C/W when mounted on a 1 in
2
pad of
2oz Cu.
b. 95
o
C/W when mounted on a
pad of 2oz Cu.
0.066 in
2
c. 110 C/W when mounted on a 0.00123
in pad of 2oz Cu.
2
o
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
NDT3055L Rev.A1
Typical Electrical Characteristics
25
I
D
, DRAIN-SOURCE CURRENT (A)
2
6.0V
4.5V
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 10V
20
5.0V
1.8
V
GS
= 4.0V
1.6
1.4
1.2
1
0.8
15
4.5V
5.0V
6.0V
8.0V
10V
4.0V
10
3.5V
5
3.0V
0
0
1
2
3
4
5
0
5
V
DS
, DRAIN-SOURCE VOLTAGE (V)
10
15
I
D
, DRAIN CURRENT (A)
20
25
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.8
DRAIN-SOURCE ON-RESISTANCE
1.6
1.4
1.2
1
0.8
0.6
-50
R
DS(ON)
, ON-RESISTANCE (OHM)
0.28
I
D
= 4.0 A
V
GS
= 10 V
I
D
= 2A
0.24
0.2
0.16
R
DS(ON)
, NORMALIZED
T
A
= 125°C
0.12
0.08
25°C
0.04
0
-25
0
25
50
75
100
125
150
2
4
6
8
10
T
J
, JUNCTION TEMPERATURE (°C)
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with
Gate-to- Source Voltage.
10
I
S
, REVERSE DRAIN CURRENT (A)
30
V
DS
= 5V
I
D
, DRAIN CURRENT (A)
8
TJ = -55°C
25°C
125°C
10 V
GS
= 0V
1
TA = 125°C
25°C
-55°C
6
0.1
0.01
4
2
0.001
0.0001
0
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage
Variation with Current and
Temperature.
NDT3055L Rev.A1
Typical Electrical Characteristics (continued)
1000
V
GS
, GATE-SOURCE VOLTAGE (V)
10
I
D
= 4A
8
V
DS
= 10V
CAPACITANCE (pF)
30V
40V
500
Ciss
200
6
Coss
100
50
4
Crss
f = 1 MHz
V
GS
= 0V
0.3
1
4
10
30
60
2
20
10
0.1
0
0
2
4
6
8
10
12
14
Q
g
, GATE CHARGE (nC)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
50
IT
LIM
N)
S(O
RD
80
I
D
, DRAIN CURRENT (A)
10
3
1
0.3
0.1
0.03
0.01
0.1
10
0u
s
1m
s
60
POWER (W)
10m
10
1s
10
s
DC
0m
s
SINGLE PULSE
R
θ
JA
=110°C/W
T
A
= 25°C
s
40
V
GS
= 10V
SINGLE PULSE
R
θ
JA
= 110
o
C/W
T
A
= 25°C
0.2
0.5
1
2
20
5
10
30
60 100
0
0.001
0.01
0.1
1
10
100
300
V
DS
, DRAIN-SOURCE VOLTAGE (V)
SINGLE PULSE TIME (SEC)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
Single Pulse
D = 0.5
0.2
0.1
0.05
0.02
0.01
R
θ
JA
(t) = r(t) * R
θ
JA
R
θ
JA
= 110 °C/W
P(pk)
t
1
t
2
0.002
0.001
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
T
J
- T
A
= P * R
JA
(t)
θ
Duty Cycle, D = t
1
/ t
2
10
100
300
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1c.
Transient thermal response will change depending on the circuit board design.
NDT3055L Rev.A1
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
E
2
CMOS
TM
FACT™
FACT Quiet Series™
FAST
®
FASTr™
GTO™
HiSeC™
DISCLAIMER
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
TinyLogic™
UHC™
VCX™
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Advance Information
Product Status
Formative or
In Design
Definition
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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