Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
General Description
The DS1856 dual, temperature-controlled, nonvolatile
(NV) variable resistors with three monitors consists of
two 256-position, linear, variable resistors; three analog
monitor inputs (MON1, MON2, MON3); and a direct-to-
digital temperature sensor. The device provides an
ideal method for setting and temperature-compensating
bias voltages and currents in control applications using
minimal circuitry. The variable resistor settings are
stored in EEPROM memory and can be accessed over
the 2-wire serial bus.
Relative to other members of the family, the DS1856 is
essentially a DS1859 with a DS1852-friendly memory
map. In particular, the DS1856 can be configured so
the 128 bytes of internal Auxiliary EEPROM memory is
mapped into Main Device Table 00h and Table 01h,
maintaining compatibility between both the
DS1858/DS1859 and the DS1852. The DS1856 also
features password protection equivalent to the DS1852,
further enhancing compatibility between the two.
Features
o
SFF-8472 Compatible
o
Five Monitored Channels (Temperature, V
CC
,
MON1, MON2, MON3)
o
Three External Analog Inputs (MON1, MON2, MON3)
That Support Internal and External Calibration
o
Scalable Dynamic Range for External Analog Inputs
o
Internal Direct-to-Digital Temperature Sensor
o
Alarm and Warning Flags for All Monitored
Channels
o
Two Linear, 256-Position, Nonvolatile Temperature-
Controlled Variable Resistors
o
Resistor Settings Changeable Every 2°C
o
Three Levels of Security
o
Access to Monitoring and ID Information
Configurable with Separate Device Addresses
o
2-Wire Serial Interface
o
Two Buffers with TTL/CMOS-Compatible Inputs and
Open-Drain Outputs
o
Operates from a 3.3V or 5V Supply
o
-40°C to +95°C Operating Temperature Range
Applications
Optical Transceivers
Optical Transponders
Instrumentation and Industrial Controls
RF Power Amps
Diagnostic Monitoring
Ordering Information
PART
DS1856E-050
DS1856E-050/T&R
DS1856B-050
RES0/RES1
RESISTANCE
(kΩ)
50/50
50/50
50/50
PIN-PACKAGE
16 TSSOP
16 TSSOP
16 CSBGA
Typical Operating Circuit
V
CC
V
CC
= 3.3V
4.7kΩ
2-WIRE
INTERFACE
Tx-FAULT
4.7kΩ
1
2
3
4
5
LOS
6
IN2
7
8
N.C.
GND
MON3
MON2
MON1
SDA
SCL
OUT1
IN1
OUT2
11 Rx POWER*
10 Tx POWER*
9 Tx BIAS*
DIAGNOSTIC
INPUTS
V
CC
H1
L1
H0
16
15
14
13
12
DECOUPLING
CAPACITOR
0.1μF
Ordering Information continued at end of data sheet.
+Denotes
lead-free package.
T&R denotes tape-and-reel package.
Note:
All devices are specified over the -40°C to +95°C tem-
perature range.
TO LASER BIAS
CONTROL
TO LASER
MODULATION
CONTROL
TOP VIEW
A
Pin Configurations
SDA 1
IN1
SCL
V
CC
H1
SCL 2
OUT1 3
L1
IN1 4
C
N.C.
IN2
OUT1
MON3
OUT2 5
IN2 6
D
GND
1
L0
2
MON1
3
MON2
4
N.C. 7
GND 8
16 V
CC
15 H1
14 L1
DS1856
L0
B
OUT2
SDA
H0
DS1856
13 H0
12 L0
11 MON3
10 MON2
9
MON1
*SATISFIES SFF-8472 COMPATIBILITY
Visit
www.maximintegrated.com/products/patents
for
product patent marking information.
CSBGA (4mm x 4mm)
1.0mm PITCH
TSSOP
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Rev 1; 2/06
DS1856
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
CC
Relative to Ground ...........-0.5V to +6.0V
Voltage Range on Inputs Relative
to Ground* ..............................................-0.5V to (V
CC
+ 0.5V)
Voltage Range on Resistor Inputs Relative
to Ground* ..............................................-0.5V to (V
CC
+ 0.5V)
Current into Resistors............................................................5mA
*Not
to exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +70°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature .......................................See IPC/JEDEC
J-STD-020A
RECOMMENDED OPERATING CONDITIONS
(T
A
= -40°C to +95°C, unless otherwise noted.)
PARAMETER
Supply Voltage
Input Logic 1 (SDA, SCL)
Input Logic 0 (SDA, SCL)
Resistor Inputs (L0, L1, H0, H1)
Resistor Current
High-Impedance Resistor Current
Input Logic Levels (IN1, IN2)
I
RES
I
ROFF
Input logic 1
Input logic 0
1.6
0.9
SYMBOL
V
CC
V
IH
V
IL
(Note 1)
(Note 2)
(Note 2)
CONDITIONS
MIN
2.85
0.7 x Vcc
-0.3
-0.3
-3
0.001
TYP
MAX
5.50
V
CC
+ 0.3
+0.3 x V
CC
V
CC
+ 0.3
+3
0.1
UNITS
V
V
V
V
mA
µA
V
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted.)
PARAMETER
Supply Current
Input Leakage
Low-Level Output Voltage
(SDA, OUT1, OUT2)
Full-Scale Input (MON1, MON2,
MON3)
Full-Scale V
CC
Monitor
I/O Capacitance
Digital Power-On Reset
Analog Power-On Reset
C
I/O
POD
POA
1.0
2.0
SYMBOL
I
CC
I
IL
V
OL1
V
OL2
3mA sink current
6mA sink current
At factory setting
(Note 4)
At factory setting (Note 5)
CONDITIONS
(Note 3)
-200
0
0
2.4875
6.5208
2.5
6.5536
MIN
TYP
1
MAX
2
+200
0.4
0.6
2.5125
6.5864
10
2.2
2.6
UNITS
mA
nA
V
V
V
pF
V
V
2
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
ANALOG RESISTOR CHARACTERISTICS
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted.)
PARAMETER
Position 00h Resistance (50kΩ)
Position FFh Resistance (50kΩ)
Position 00h Resistance (30kΩ)
Position FFh Resistance (30kΩ)
Position 00h Resistance (20kΩ)
Position FFh Resistance (20kΩ)
Position 00h Resistance (10kΩ)
Position FFh Resistance (10kΩ)
Position 00h Resistance (2.5kΩ)
Position FFh Resistance (2.5kΩ)
Absolute Linearity
Relative Linearity
Temperature Coefficient
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
(Note 6)
(Note 7)
(Note 8)
CONDITIONS
MIN
0.65
40
0.165
22.5
0.20
15
0.075
7.5
0.1
2.0
-2
-1
50
TYP
1.0
50
0.275
30
0.40
20
0.125
10
0.175
2.50
MAX
1.35
60
0.400
37.5
0.55
25
0.200
12.5
0.250
3.0
+2
+1
UNITS
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
LSB
LSB
ppm/°C
ANALOG VOLTAGE MONITORING
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted.)
PARAMETER
Input Resolution
Supply Resolution
Input/Supply Accuracy
(MON1, MON2, MON3, V
CC
)
Update Rate for MON1, MON2,
MON3, Temp, or V
CC
Input/Supply Offset
(MON1, MON2, MON3, V
CC
)
SYMBOL
ΔVMON
ΔV
CC
A
CC
t
frame
V
OS
(Note 14)
At factory setting
CONDITIONS
MIN
TYP
610
1.6
0.25
47
0
0.5
60
5
MAX
UNITS
µV
mV
% FS
(full scale)
ms
LSB
DIGITAL THERMOMETER
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted.)
PARAMETER
Thermometer Error
SYMBOL
T
ERR
CONDITIONS
-40°C to +95°C
MIN
TYP
MAX
±3.0
UNITS
°C
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= 2.85V to 5.5V)
PARAMETER
EEPROM Writes
SYMBOL
CONDITIONS
+70°C (Note 14)
MIN
50,000
TYP
MAX
UNITS
Writes
Maxim Integrated
3
DS1856
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted. See Figure 6.)
PARAMETER
SCL Clock Frequency (Note 9)
Bus Free Time Between STOP and
START Condition (Note 9)
Hold Time (Repeated)
START Condition (Notes 9, 10)
LOW Period of SCL Clock (Note 9)
HIGH Period of SCL Clock (Note 9)
Data Hold Time (Notes 9, 11, 12)
Data Setup Time (Note 9)
START Setup Time (Note 9)
Rise Time of Both SDA and SCL
Signals (Note 13)
Fall Time of Both SDA and SCL
Signals (Note 13)
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
EEPROM Write Time
SYMBOL
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
HD:DAT
t
SU:DAT
t
SU:STA
t
R
t
F
t
SU:STO
C
B
t
W
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
(Note 13)
10
CONDITIONS
MIN
0
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
0
100
250
0.6
4.7
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
0.6
4.0
400
20
300
1000
300
300
0.9
TYP
MAX
400
100
UNITS
kHz
µs
µs
µs
µs
µs
ns
µs
ns
ns
µs
pF
ms
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
All voltages are referenced to ground.
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
SDA and SCL are connected to V
CC
and all other input signals are connected to well-defined logic levels.
Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the volt-
age on the inputs is greater than full scale.
This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum V
CC
voltage.
Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
See the
Typical Operating Characteristics.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000ns + 250ns = 1250ns
before the SCL line is released.
4
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
Note 10:
After this period, the first clock pulse is generated.
Note 11:
The maximum t
HD:DAT
only has to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 12:
A device must internally provide a hold time of at least 300ns for the SDA signal (see the V
IH MIN
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 13:
C
B
—total capacitance of one bus line, timing referenced to 0.9 x V
CC
and 0.1 x V
CC
.
Note 14:
Guaranteed by design.
Typical Operating Characteristics
(V
CC
= 5.0V, T
A
= +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
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