2 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter
if burst is desired.
4/15/02; v.1.9
Alliance Semiconductor
P. 3 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Functional description
The AS7C33256PFS32A and AS7C33256PFS36A are high-performance CMOS 8-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 262,144 words x 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given
technology.
Timing for these devices is compatible with existing Pentium
®
synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC
™
1
-based systems in computing, datacomm, instrumentation, and telecommunications systems.
Fast cycle times of 6/6.6/7.5/10 ns with clock access times (t
CD
) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.
Two-chip enable and three-chip enable (CE) inputs permit versatility and easy memory expansion. Burst operation is initiated in one of two
ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally
generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High.
Burst mode is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium
®
count sequence. With
LBO driven LOW, the device uses a linear count sequence suitable for PowerPC
™
and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to
the next burst address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
• Master chip enable CE0 blocks ADSP, but not ADSC.
AS7C33256PFS32A and AS7C33256PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate
at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package and in a 119-pin 14 × 20 mm BGA package.
Capacitance
Parameter
Input capacitance
I/O capacitance
GWE
L
H
H
H
Symbol
C
IN
C
I/O
Signals
Address and control pins
I/O pins
BWE
X
L
H
L
BWn
X
L
X
H
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
WEn
T
T
F*
F
*
Max
5
7
Unit
pF
pF
Write enable truth table (per byte)
.H\
X = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d;
WE, WEn
= internal write signal.
Burst order table
Interleaved Burst Order
Starting Address
First increment
Second increment
Third increment
00
01
10
11
LBO=1
01
10
00
11
11
00
10
01
11
10
01
00
Starting Address
First increment
Second increment
Third increment
Linear Burst Order
00
01
10
11
LBO=0
01
10
10
11
11
00
00
01
11
00
01
10
1 PowerPC
™
is a trademark International Business Machines Corporation.
4/15/02; v.1.9
Alliance Semiconductor
P. 4 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Signal descriptions
Signal
CLK
A0–A17
DQ[a,b,c,d]
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b,c,d]
OE
LBO
FT
ZZ
I/O
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
Properties
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
STATIC
ASYNC
Description
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
Advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]
control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This signal is internally pulled High.
Flow-through mode.When low, enables single register flow-through mode. Connect to
V
DD
if unused or for pipelined operation.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
Symbol
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
Min
–0.5
–0.5
–0.5
–
–
–65
–65
Max
+4.6
V
DD
+ 0.5
V
DDQ
+ 0.5
1.8
50
+150
+135
Unit
V
V
V
W
mA
o
C
o
C
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
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