®
RT8886A
2-Phase Controller with Dual Integrated Drivers for VR12.5
and VR12.6 Mobile CPU Core Power Supply
General Description
The RT8886A is a two phase CPU power controller with
dual integrated drivers for VR12.5 and VR12.6 compliant.
The RT8886A adopts the G-NAVP
TM
(Green Native AVP)
which is Richtek's proprietary topology derived from finite
DC gain of EA amplifier with current mode control, making
it easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning). Based on the G-
NAVP
TM
topology, the RT8886A also features a quick
response mechanism for optimized AVP performance
during load transient. The RT8886A supports mode
transition function with various operating states. A Serial
VID (SVID) interface is built in the RT8886A to
communicate with Intel VR12.5 and VR12.6 compliant
CPU. The RT8886A supports VID on-the-fly function with
different slew rates. By utilizing the G-NAVP
TM
topology,
the operating frequency of the RT8886A varies with VID,
load current and input voltage to further enhance the
efficiency even in CCM. Besides the G-NAVP
TM
, the
CCRCOT (Constant Current Ripple Constant On Time)
technology provides superior output voltage ripple over
the entire input/output range. The built-in high accuracy
DAC converts the SVID code ranging from 0.5V to 3.04V
with 10mV per step. The RT8886A integrates a high
accuracy ADC for platform setting functions, such as no-
load offset and over-current protection level. The RT8886A
provides VR ready output signals. It also features complete
fault protection functions including Over-Voltage (OV),
Under-Voltage (UV), Negative-Voltage (NV), Over-Current
(OC) and Under-Voltage Lockout (UVLO). The RT8886A
is available in the WQFN-32L 4x4 small foot print package.
Features
Intel VR12.5 and VR12.6 Serial VID Interface
Compatible Power Management States
2/1 Phase PWM Controller with Dual Integrated
Drivers
G-NAVP
TM
Topology
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Built-in ADC for Platform Programming
Accurate Current Balance
System Thermal Compensated AVP
Diode Emulation Mode at Light Load Condition for
Single Phase
Fast transient Response
VR Ready Indicator
Thermal Throttling
Current Monitor Output
OVP, UVP, OCP, UVLO
Programmable DVID Slew Rate
DVID Enhancement
Small 32-Lead WQFN Package
RoHS Compliant and Halogen Free
Simplified Application Circuit
To PCH
RT8886A
VR_RDY
PHASE1
VR_HOT
VCLK
VDIO
ALERT
PHASE2
MOSFET
MOSFET
V
CORE
To CPU
Copyright
©
2013 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
www.richtek.com
1
RT8886A
Applications
Marking Information
15= : Product Code
VR12.5 and VR12.6 Intel Core Supply
Notebook Multi-phase CPU Core Supply
AVP Step-Down Converter
15=YM
DNN
YMDNN : Date Code
Ordering Information
RT8886A
Package Type
QW : WQFN-32L 4x4 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
½
Pin Configurations
(TOP VIEW)
PHASE2
LGATE2
PVCC
LGATE1
PHASE1
UGATE1
BOOT1
VR_RDY
32 31 30 29 28 27 26 25
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
½
UGATE2
BOOT2
EN
ISEN2P
ISEN2N
ISEN1N
ISEN1P
IMON
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
21
20
33
19
18
17
GND
TONSET
VCLK
ALERT
VDIO
VR_HOT
TSEN
IBIAS
SET3
Functional Pin Description
Pin No.
3
6, 5
7, 4
8
9
10
11
12
13
14
Pin Name
EN
ISEN [1:2] N
ISEN [1:2] P
IMON
VREF
COMP
FB
VSEN
RGND
VCC
VR Enable Control Input.
Negative Current Sense Inputs of Channel 1 and 2.
Positive Current Sense Inputs of Channel 1 and 2.
CPU CORE Current Monitor Output. This pin outputs a voltage proportional to
the output current. Don’t connect a bypass capacitor from this pin to GND or the
VREF pin.
Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the
output voltage of the IMON pin.
CORE VR Compensation Node. This pin is error amplifier output pin.
Negative Input of the Error Amplifier. This pin is for output voltage feedback to
controller.
VR Voltage Sense Input. This pin is connected to the terminal of VR output
voltage.
Return Ground for VR. This pin is the negative node of the differential remote
voltage sensing.
Supply Voltage Input. Connect this pin to 5V and place a decoupling capacitor
2.2F at least. The decoupling capacitor should be placed as close to the PWM
controller as possible.
1 Platform Setting. Platform can use this pin to set DVID compensation time,
RSET, DVID compensation width and OCS.
st
Pin Function
15
SET1
Copyright
©
2013 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
VREF
COMP
FB
VSEN
RGND
VCC
SET1
SET2
WQFN-32L 4x4
DS8886A-00 November 2013
RT8886A
Pin No.
16
Pin Name
nd
Pin Function
2 Platform Setting. Platform can use this pin to set ICCMAX, QRTH and
QRWIDTH.
3 Platform Setting. Platform can use this to set Anti-ov ershoot function, zero
load-line, DVID slew rate, RSET selection at PS1, Anti-Overshoot enhancem ent
and ZCD threshold.
Internal Bias Current Setting. Connect a 100k resistor from this pin tied to
GND to set the internal current. Don’t connect a bypass pass capacitor from this
pin to GND.
Thermal Sense Input for CORE VR.
Thermal Monitor Output. (Active Low)
VR and CPU Data Transmission Interface.
SVID Alert. (Active Low).
Synchronous Clock from the CPU.
On-time Setting. An on-time setting resistor is connected from this pin to input
voltage.
VR Ready Indicator.
Driver Power. Connect this pin to GND by a minimum 2.2F ceramic capacitor.
Bootstrap Supply for High-Side Gate Driver.
High-Side Gate Drive Output. Connect the pin to the Gate of high-side MOSFET.
Switch Node of High-Side Driver. Connect the pin to high-side MOSFET Source
with the low-side MOSFET Drain and the inductor.
Low-Side Gate Drive Output. This pin drives the Gate of low-side MOSFET.
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
rd
SET2
17
SET3
18
19
20
21
22
23
24
25
30
26, 2
27, 1
28, 32
29, 31
33
(Exposed Pad)
IBIAS
TSEN
VR_HOT
VDIO
ALERT
VCLK
TONSET
VR_RDY
PVCC
BOOT [1:2]
UGATE [1:2]
PHASE [1:2]
LGATE [1:2]
GND
Copyright
©
2013 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
www.richtek.com
3
RT8886A
Function Block Diagram
VR_RDY
VR_HOT
ALERT
VSEN
TSEN
VCLK
SET1
SET2
SET3
VDIO
VCC
UVLO
EN
IMONI
MUX
IBIAS
VCC
ADC
SVID Interface
Configuration
Registers Control
Logic
GND
From Control Logic
RGND
DAC
QR,
QRWIDTH,
OCP_TDC,
RSET
DAC
TON
Load Line
Current Balance
Loop Control
Protection Logic
TONSET
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
UGATE2
PHASE2
LGATE2
Soft-Start & Slew
Rate Control
FB
COMP
ERROR
AMP
VSET
+
-
Offset
Cancellation
+
PWM
CMP
TON
GEN
PWM1
Dual
Phase
Driver
PWM2
+
1/4
Ai
RSET
IMON Filter
IMONI
+
-
Current mirror
ISEN1P
ISEN1N
+
-
IB1
Current mirror
QR
QRWIDTH
TON
ISEN2P
ISEN2N
+
-
Current Balance
x100%
IB1
x100%
IB2
IB2
IMONI
Current Balance
To Protection Logic
OC
OCS_TDC
-
VSEN
OV/UV/NV
IMON VREF
Copyright
©
2013 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS8886A-00 November 2013
RT8886A
Operation
The RT8886A adopts the G-NAVP
TM
(Green Native AVP)
which is Richtek's proprietary topology derived from finite
DC gain of EA amplifier with current mode control, making
it easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning).
The G-NAVP
TM
controller is one type of current mode
constant on-time control with DC offset cancellation. The
approach can not only improve DC offset problem for
increasing system accuracy but also have fast transient
response. When current feedback signal reaches COMP
signal, the RT8886A generates an on-time width to achieve
PWM modulation.
TON GEN
Generate the PWM signal sequentially according to the
phase control signal from the Loop Control Protection
Logic.
SVID Interface/Configuration Registers/Control
Logic
The interface that receives the SVID signal from CPU and
sends the relative signals to Loop Control Protection Logic
to execute the action by CPU.
The registers save the pin setting data from ADC output.
The Control Logic controls the ADC timing and generates
the digital code of the VID that is relative to VSEN.
Loop Control Protection Logic
It controls the power on sequence, and the protection
behavior, and the operational phase number.
Current Balance
Each phase current sense signal is sent to the current
balance circuit which adjusts the on-time of each phase
to optimize current sharing.
Offset Cancellation
Cancel the current/voltage ripple issue to get the accurate
VSEN.
UVLO
Detect the PVCC and VCC voltage and issue POR signal
as they are high enough.
DAC
Generate an analog signal according to the digital code
generated by Control Logic.
Soft-Start & Slew Rate Control
Control the Dynamic VID slew rate of VSET according to
the SetVID fast or SetVID slow.
Copyright
©
2013 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8886A-00 November 2013
www.richtek.com
5
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