电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

LTC2000A

产品描述16-/14-/11-bit 2.7gspsdacs
产品类别半导体    模拟混合信号IC   
文件大小2MB,共52页
制造商Linear ( ADI )
官网地址http://www.analog.com/cn/index.html
下载文档 全文预览

LTC2000A概述

16-/14-/11-bit 2.7gspsdacs

文档预览

下载PDF文档
LTC2000A
16-/14-/11-Bit 2.7Gsps
DACs
Features
n
n
n
n
n
n
Description
The
LTC
®
2000A
is a family of 16-/14-/11-bit 2.7Gsps
current steering DACs with exceptional spectral purity.
The single (1.35Gsps mode) or dual (2.7Gsps mode) port
source synchronous LVDS interface supports data rates of
up to 1.35Gbps using a 675MHz DDR data clock, which
can be either in quadrature or in phase with the data. An
internal synchronizer automatically aligns the data with
the DAC sample clock.
Additional features such as pattern generation, LVDS
loopout and junction temperature sensing simplify system
development and testing.
A serial peripheral interface (SPI) port allows configura-
tion and read back of internal registers. Operating from
1.86V and 3.3V supplies, the LTC2000A consumes 2.41W
at 2.7Gsps and 1.43W at 1.35Gsps.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 8330633.
n
n
n
80dBc SFDR at 50MHz f
OUT
>68dBc SFDR from DC to 1080MHz f
OUT
40mA Nominal Full-Scale, ±1V Output Compliant
10mA to 60mA Adjustable Full-Scale Current Range
Single or Dual Port DDR LVDS and DHSTL Interface
Low Latency (7.5 Cycles for Single Port,
11 Cycles for Dual Port)
>78dBc 2-Tone IMD from DC to 1000MHz f
OUT
–156dBc/Hz Additive Phase Noise at 1MHz Offset for
65MHz f
OUT
170-Lead (9mm
×
15mm) BGA Package
applications
n
n
n
n
n
n
Broadband Communication Systems
DOCSIS CMTS
Direct RF Synthesis
Radar
Instrumentation
Automatic Test Equipment
Block Diagram
TSTP/N
JUNCTION
TEMPERATURE
PATTERN
GENERATOR
PD
CS
SCK SDI
SPI
SDO
SV
DD
SFDR vs f
OUT
, f
DAC
= 2.7Gsps
100
I
OUTP
50
SFDR (dBc)
DIGITAL AMPLITUDE = 0dBFS
I
OUTFS
= 40mA
DAP/N[15:0]
DDR DATA FLIP-FLOPS
90
LVDS RECEIVERS
4:1
16-BIT DAC
50
I
OUTN
DBP/N[15:0]
80
70
GAIN
ADJUST
DCKIP/N
DELAY
ADJUST
CLK DIVIDER
÷2 OR ÷4
AV
DD18
DV
DD18
AV
DD33
DV
DD33
GND
CLOCK
SYNC
CLK
RECEIVER
CKP/N
FSADJ
REFIO
10k
REF
2000A BD
60
50
DCKOP/N
0
200
400
600
800
f
OUT
(MHz)
1000
1200
2000A TA01b
2000af
For more information
www.linear.com/LTC2000A
1

技术资料推荐更多

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2888  329  1054  2374  357  7  29  46  10  14 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved