Si53322
1:2
L O W J I T T E R LVPECL CLOCK BUFFER
(>1.25 GH
Z
)
Features
2 LVPECL outputs
Ultra-low additive jitter: 55 fs rms
Wide frequency range: dc to
1250 MHz
Universal input stage accepts
differential or LVCMOS clock
V
DD
: 2.5 / 3.3 V
Small size: 16-QFN (3 mm x
3 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Ordering Information:
See page 17.
Pin Assignments
GND
NC
NC
14
The Si53322 is an ultra-low-jitter two-output LVPECL buffer. Utilizing
Silicon Laboratories’ advanced fan-out clock technology, the Si53322
guarantees low additive jitter, low skew, and low propagation delay
variability from dc to 1250 MHz.
The Si53322 features minimal cross-talk and excellent supply noise
rejection, simplifying low-jitter clock distribution in noisy environments.
GND
NC
NC
NC
1
2
3
4
5
6
7
8
NC
13
12
Description
16
EXPOSED
GND
PAD
15
Q1
Q1
Q0
Q0
11
10
9
Functional Block Diagram
V
DD
CLK
VDD
Power
Supply
Filtering
Patents pending
Q0
CLK
CLK
Q0
Q1
Q1
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
CLK
NC
Si53322
Si53322
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.4. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.6. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Pin Description: 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1. Si53322 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.0
2
Si53322
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range
Symbol
T
A
V
DD
LVPECL
Test Condition
Min
–40
2.38
2.97
Typ
—
2.5
3.3
Max
85
2.63
3.63
Unit
°C
V
V
Table 2. Input Clock Specifications
(2.5 V
5%, or 3.3 V
10%, T
A
=–40 to 85 °C)
Parameter
Differential Input Common
Mode Voltage
Differential Input Swing
(peak-to-peak)
LVCMOS Input High Voltage
LVCMOS Input Low Voltage
Input Capacitance
Symbol
V
CM
V
IN
V
IH
V
IL
C
IN
V
DD
= 2.5 V
5%, 3.3 V
10%
V
DD
= 2.5 V
5%, 3.3 V
10%
CLK0 and CLK1 pins with
respect to GND
Test Condition
V
DD
= 2.5 V
5%, 3.3 V
10%
Min
0.05
0.2
V
DD
x 0.7
—
—
Typ
—
—
—
—
5
Max
—
2.2
—
V
DD
x 0.3
—
Unit
V
V
V
V
pF
Table 3. DC Common Characteristics
(2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Supply Current
Symbol
I
DD
Test Condition
Measured using ac-
coupled termination
shown in Figure 6
CLK_SEL
CLK_SEL
CLK_SEL
Min
—
Typ
210
Max
—
Unit
mA
Input High Voltage
Input Low Voltage
Internal Pull-down
Resistor
V
IH
V
IL
R
DOWN
0.8 x V
DD
—
—
—
—
25
—
0.2 x V
DD
—
V
V
k
Rev. 1.0
3
Si53322
Table 4. Output Characteristics (LVPECL)
(V
DD
= 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Output DC Common Mode
Voltage
Single-Ended
Output Swing*
Symbol
V
COM
V
SE
Test Condition
Min
V
DD
– 1.595
0.40
Typ
—
0.80
Max
V
DD
– 1.245
1.050
Unit
V
V
*Note:
Unused outputs can be left floating. Do not short unused outputs to ground.
Table 5. AC Characteristics
(V
DD
= 2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Frequency
Duty Cycle
Note:
50% input duty cycle.
Symbol
F
D
C
D
C
SR
Test Condition
Min
dc
Typ
—
50
50
—
Max
1250
53
55
—
Unit
MHz
%
%
V/ns
20/80% T
R
/T
F
<10% of period
(Differential input clock)
20/80% T
R
/T
F
<10% of period
(Single-Ended input clock)
Required to meet prop delay and
additive jitter specifications
(20–80%)
20–80%
47
45
0.75
Duty Cycle
Note:
50% input duty cycle.
Minimum Input Clock
Slew Rate
Output Rise/Fall Time
T
R
/T
F
T
W
T
PLH,
T
PHL
T
SK
T
PS
PSRR
—
—
350
ps
Minimum Input Pulse
Width
Propagation Delay
Output to Output Skew
1
Part to Part Skew
2
Power Supply Noise
Rejection
3
360
600
—
Differential
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
—
—
—
—
—
—
800
20
—
–70
–65
–60
–57.5
—
1000
50
150
—
—
—
—
ps
ps
ps
ps
dBc
dBc
dBc
dBc
Notes:
1.
Output-to-output skew specified for outputs with identical configuration.
2.
Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
3.
Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V
DD
(3.3 V = 100 mV
PP
) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
4
Rev. 1.0
Si53322
Table 6. Additive Jitter, Differential Clock Input
V
DD
Input
1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)
3
Typ
Max
Freq
(MHz)
Clock Format
Amplitude
V
IN
(Single-Ended,
Peak-to-Peak)
Differential
Clock Format
20%-80% Slew
Rate (V/ns)
3.3
3.3
2.5
2.5
725
156.25
725
156.25
Differential
Differential
Differential
Differential
0.15
0.5
0.15
0.5
0.637
0.458
0.637
0.458
LVPECL
LVPECL
LVPECL
LVPECL
55
160
55
145
95
185
95
185
Notes:
1.
For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2.
AC-coupled differential inputs.
3.
Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
Table 7. Additive Jitter, Single-Ended Clock Input
V
DD
Input
1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)
3
Typ
Max
Freq
(MHz)
Clock Format
Amplitude
V
IN
(single-ended,
peak to peak)
SE 20%-80%
Slew Rate
(V/ns)
Clock Format
3.3
2.5
156.25
156.25
Single-ended
Single-ended
2.18
2.18
1
1
LVPECL
LVPECL
160
145
185
185
Notes:
1.
For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2.
DC-coupled single-ended inputs.
3.
Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
PSPL 5310A
CLK SYNTH
SMA103A
Balun
Si533xx
DUT
CLKx
50
PSPL 5310A
AG E5052 Phase Noise
Analyzer
50ohm
50
/CLKx
Balun
Figure 1. Differential Measurement Method Using a Balun
Rev. 1.0
5
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