Si53321
1 : 1 0 L
OW
J
I T T E R
LVPECL C
LOCK
B
U F F E R
W I T H
2:1 I
NPUT
M
UX
(< 1.25 GH
Z
)
Features
10 LVPECL outputs
Ultra-low additive jitter: 45 fs rms typ
Wide frequency range: dc to
1.25 GHz
Input compatible with LVPECL,
LVDS, CML, HCSL, LVCMOS
2:1 input mux
Low output-output skew: 25 ps (typ)
RoHS compliant, Pb-free
32-QFN, 32-eLQFP
Industrial temperature range:
–40 to +85°C
Footprint-compatible with
MC100LVEP111, CDCLVP111,
MAX9311, ICS853S111BI,
ICS85310-1
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Ordering Information:
See page 19.
Pin Assignments (Top View)
VDD
Q0
Q0
VDD
25
24
23
22
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
21
20
19
18
17
9
10
11
12
13
14
15
16
VDD
Q1
Q1
Q2
27
Q7
Q2
26
Q7
Description
The Si53321 is an ultra-low jitter ten output differential buffer. The Si53321
features a 2:1 input mux, making it ideal for redundant clocking applications. The
Si53321 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from dc to 1.25 GHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53321 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments.
VDD
CLK_SEL
CLK0
CLK0
NC
CLK1
CLK1
GND
1
2
3
4
5
6
7
8
32
31
30
29
28
Exposed
GND Pad
Functional Block Diagram
Q0
VDD
Q8
Q9
Q9
Q8
Q0
Q0
Q1
Q1
Q2
VDD
Power
Supply
Filtering
Q1
Q1
Q2
Q2
Q3
Q3
VDD
CLK_SEL
CLK0
CLK0
NC
CLK1
CLK1
GND
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
Q2
Q0
VDD
VDD
25
24 Q3
23 Q3
22 Q4
21 Q4
20 Q5
19 Q5
18 Q6
17 Q6
16
VDD
CLK0
CLK0
CLK1
CLK1
CLK_SEL
0
Q4
Q4
Q5
Exposed
GND Pad
1
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
9
VDD
10
Q9
11
Q9
12
Q8
13
Q8
14
Q7
15
Q7
Patents pending
GND
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si53321
Si53321
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3. Input Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.4. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.5. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.7. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.8. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Pin Description: 32-eLQFP, 32-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1. 32-eLQFP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2. 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.1. 32-eLQFP Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2. 32-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
7.1. Si53321 32-eLQFP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2. Top Marking Explanation (32-eLQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3. Si53321 32-QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.4. Top Marking Explanation (32-QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2
Rev. 1.0
Si53321
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range
Symbol
T
A
V
DD
LVPECL
Test Condition
Min
–40
2.38
2.97
Typ
—
2.5
3.3
Max
85
2.63
3.63
Unit
°C
V
V
Table 2. Input Clock Specifications
(2.5 V
5%, or 3.3 V
10%, T
A
=–40 to 85 °C)
Parameter
Differential Input Common
Mode Voltage
Differential Input Swing
(peak-to-peak)
LVCMOS Input High Voltage
LVCMOS Input Low Voltage
Input Capacitance
Symbol
V
CM
V
IN
V
IH
V
IL
C
IN
V
DD
= 2.5 V
5%, 3.3 V
10%
V
DD
= 2.5 V
5%, 3.3 V
10%
CLK0 and CLK1 pins with
respect to GND
Test Condition
V
DD
= 2.5 V
5%, 3.3 V
10%
Min
0.05
0.2
V
DD
x 0.7
—
—
Typ
—
—
—
—
5
Max
—
2.2
—
V
DD
x 0.3
—
Unit
V
V
V
V
pF
Table 3. DC Common Characteristics
(2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Supply Current
Symbol
I
DD
Test Condition
Measured using ac-
coupled termination
shown in Figure 6
CLK_SEL
CLK_SEL
CLK_SEL
Min
—
Typ
440
Max
—
Unit
mA
Input High Voltage
Input Low Voltage
Internal Pull-down
Resistor
V
IH
V
IL
R
DOWN
0.8 x V
DD
—
—
—
—
25
—
0.2 x V
DD
—
V
V
k
Rev. 1.0
3
Si53321
Table 4. Output Characteristics (LVPECL)
(V
DD
= 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Output DC Common Mode
Voltage
Single-Ended
Output Swing*
Symbol
V
COM
V
SE
Test Condition
Min
V
DD
– 1.595
0.40
Typ
—
0.80
Max
V
DD
– 1.245
1.050
Unit
V
V
*Note:
Unused outputs can be left floating. Do not short unused outputs to ground.
Table 5. AC Characteristics
(V
DD
= 2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Frequency
Duty Cycle
Note:
50% input duty cycle.
Symbol
F
D
C
D
C
SR
Test Condition
Min
dc
Typ
—
50
50
—
Max
1250
53
55
—
Unit
MHz
%
%
V/ns
20/80% T
R
/T
F
<10% of period
(Differential input clock)
20/80% T
R
/T
F
<10% of period
(Single-Ended input clock)
Required to meet prop delay and
additive jitter specifications
(20–80%)
20–80%
47
45
0.75
Duty Cycle
Note:
50% input duty cycle.
Minimum Input Clock
Slew Rate
Output Rise/Fall Time
Minimum Input Pulse
Width
Propagation Delay
Output to Output Skew
1
Part to Part Skew
2
Power Supply Noise
Rejection
3
T
R
/T
F
T
W
T
PLH,
T
PHL
T
SK
T
PS
PSRR
—
360
600
—
—
—
800
25
—
–65
–62.5
–60
–55
350
—
1000
60
150
—
—
—
—
ps
ps
ps
ps
ps
dBc
dBc
dBc
dBc
Differential
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
—
—
—
—
—
Notes:
1.
Output-to-output skew specified for outputs with identical configuration.
2.
Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
3.
Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V
DD
(3.3 V = 100 mV
PP
) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
4
Rev. 1.0
Si53321
Table 6. Additive Jitter, Differential Clock Input
V
DD
Input
1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)
3
Typ
Max
Freq
(MHz)
Clock Format
Amplitude
V
IN
(Single-Ended,
Peak-to-Peak)
Differential
Clock Format
20%-80% Slew
Rate (V/ns)
3.3
3.3
2.5
2.5
725
156.25
725
156.25
Differential
Differential
Differential
Differential
0.15
0.5
0.15
0.5
0.637
0.458
0.637
0.458
LVPECL
LVPECL
LVPECL
LVPECL
45
160
45
145
65
185
65
185
Notes:
1.
For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2.
AC-coupled differential inputs.
3.
Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
Table 7. Additive Jitter, Single-Ended Clock Input
V
DD
Input
1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)
3
Typ
Max
Freq
(MHz)
Clock Format
Amplitude
V
IN
(single-ended,
peak to peak)
SE 20%-80%
Slew Rate
(V/ns)
Clock Format
3.3
2.5
156.25
156.25
Single-ended
Single-ended
2.18
2.18
1
1
LVPECL
LVPECL
160
145
185
185
Notes:
1.
For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2.
DC-coupled single-ended inputs.
3.
Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
PSPL 5310A
CLK SYNTH
SMA103A
Balun
Si533xx
DUT
CLKx
50
PSPL 5310A
AG E5052 Phase Noise
Analyzer
50ohm
/CLKx
50
Balun
Figure 1. Differential Measurement Method Using a Balun
Rev. 1.0
5
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