Si53156
PCI-E
XPRESS
G
EN
1, G
EN
2, G
EN
3,
F
ANOUT
B
UFFER
Features
AND
G
EN
4
PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock compliant
Supports Serial ATA (SATA) at
100 MHz
100–210 MHz operation
Low power, push pull, differential
output buffers
Internal termination for maximum
integration
Dedicated output enable pin for each
output
Six PCI-Express buffered clock
outputs
Clock input spread tolerable
Supports LVDS outputs
I
2
C support with readback
capabilities
Extended temperature:
–40 to 85
o
C
3.3 V power supply
32-pin QFN package
Applications
Network attached storage
Multi-function printers
Ordering Information:
See page 17.
Pin Assignments
CKPWRGD_PDB*
Wireless access point
Routers
Description
DIFFIN
The Si53156 is a spread spectrum tolerant PCIe clock buffer that can source six
PCIe clocks simultaneously. The device has six hardware output enable control
inputs for enabling the respective differential outputs on the fly. The device also
features output enable control through I
2
C communication. I
2
C programmability is
also available to dynamically control skew, edge rate and amplitude on the true,
compliment, or both differential signals on the clock outputs. This control feature
enables optimal signal integrity as well as optimal EMI signature on the clock
outputs. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe
Clock Jitter Tool. Download it for free at
www.silabs.com/pcie-learningcenter.
SDATA
26
DIFFIN
OE1*
OE0*
32
VDD
OE2*
VDD
OE3*
OE4*
OE5*
NC
VDD
1
2
3
4
5
6
7
8
9
31
30
29
VDD
28
27
SCLK
25
24 VDD
23 DIFF5
22 DIFF5
21 VDD
20 DIFF4
19 DIFF4
18 DIFF3
17 DIFF3
16
33
GND
DIFF1
DIFF0
DIFF0
DIFF1
DIFF2
VDD
*Note:
Internal 100 kohm pull-up.
DIFF0
DIFF1
DIFF2
DIFFIN
DIFFIN
DIFF3
DIFF4
DIFF5
Patents pending
SCLK
SDATA
OE [5:0]
Control & Memory
Control
RAM
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
DIFF2
VDD
Functional Block Diagram
10
11
12
13
14
15
Si53156
Si53156
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Pin Descriptions: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Rev. 1.1
3
Si53156
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
3.3 V Operating Voltage
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Leakage Current
Input Low Leakage Current
3.3 V Output High Voltage
(Single-Ended Outputs)
3.3 V Output Low Voltage
(Single-Ended Outputs)
High-impedance Output
Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Power Down Current
Dynamic Supply Current in
Fanout Mode
Symbol
VDD core
V
IH
V
IL
V
IHI2C
V
ILI2C
I
IH
I
IL
V
OH
V
OL
I
OZ
C
IN
C
OUT
L
IN
I
DD
_
PD
I
DD_3.3V
Differential clocks with 5”
traces and 2 pF load, fre-
quency at 100 MHz
Test Condition
3.3 ± 5%
Control input pins
Control input pins
SDATA, SCLK
SDATA, SCLK
Except internal pull-down
resistors, 0 < V
IN
< V
DD
Except internal pull-up
resistors, 0 < V
IN
< V
DD
I
OH
= –1 mA
I
OL
= 1 mA
Min
3.135
2.0
V
SS
– 0.3
2.2
—
—
–5
2.4
—
–10
1.5
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
3.465
V
DD
+ 0.3
0.8
—
1.0
5
—
—
0.4
10
5
6
7
1
45
Unit
V
V
V
V
V
A
A
V
V
A
pF
pF
nH
mA
mA
4
Rev. 1.1
Si53156
Table 2. AC Electrical Specifications
Parameter
DIFFIN at 0.7 V
Input Frequency Range
Rising and Falling Slew Rates for
Each Clock Output Signal in a
Given Differential Pair
Differential Input High Voltage
Differential Input Low Voltage
Crossing Point Voltage at 0.7 V
Swing
Vcross Variation over all edges
Differential Ringback Voltage
Time before ringback allowed
Absolute maximum input voltage
Absolute minimum input voltage
Duty Cycle for Each Clock Output
Signal in a Given
Differential Pair
Rise/Fall Matching
DIFF at 0.7 V
Duty Cycle
Clock Skew
Additive Peak Jitter
Additive PCIe Gen 2 Phase Jitter
Additive PCIe Gen 3 Phase Jitter
Additive PCIe Gen 4 Phase Jitter
Additive Cycle to Cycle Jitter
Long-term Accuracy
Rising/Falling Slew rate
Crossing Point Voltage at 0.7 V
Swing
T
DC
T
SKEW
Pk-Pk
RMS
GEN2
RMS
GEN3
RMS
GEN4
T
CCJ
L
ACC
T
R
/ T
F
V
OX
10 kHz < F < 1.5 MHz
1.5 MHz< F < Nyquist Rate
Includes PLL BW 2–4 MHz
(CDR = 10 MHz)
PCIe Gen 4
Measured at 0 V differential
Measured at 0 V differential
Measured differentially from
±150 mV
Measured at 0 V differential
Measured at 0 V differential
45
—
0
0
0
0
—
—
—
2.5
300
—
—
—
—
—
—
—
—
—
—
—
55
50
10
0.5
0.5
0.10
0.10
50
100
8
550
%
ps
ps
ps
ps
ps
ps
ps
ppm
V/ns
mV
f
in
T
R
/T
F
Single ended measurement:
V
OL
= 0.175 to V
OH
= 0.525 V
(Averaged)
100
0.6
—
—
210
4
MHz
V/ns
Symbol
Condition
Min
Typ
Max
Unit
V
IH
V
IL
V
OX
V
OX
V
RB
T
STABLE
V
MAX
V
MIN
T
DC
Measured at crossing point V
OX
Single-ended measurement
Single-ended measurement
150
—
250
—
–100
500
—
–0.3
45
—
—
—
—
—
—
—
—
—
—
–150
550
140
100
—
1.15
—
55
mV
mV
mV
mV
mV
ps
V
V
%
T
RFM
Determined as a fraction of
2 x (T
R
– T
F
)/(T
R
+ T
F
)
—
—
20
%
Notes:
1.
Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2.
Download the Silicon Labs PCIe Clock Jitter Tool at
www.silabs.com/pcie-learningcenter.
Rev. 1.1
5
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