S i 5 3 11 2 - A 0 3 A
DB1200ZL 12-O
UTPUT
PCI
E
G
EN
3 B
UFFER
Features
Twelve 0.7 V low-power, push-
pull, HCSL-compatible
PCIe Gen 3 outputs
Individual OE HW pins for each
output clock
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
PLL bandwidth SW SMBUS
programming overrides the latch
value from HW pin
9 selectable SMBUS addresses
SMBus address configurable to
allow multiple buffers in a single
control network 3.3 V supply
voltage operation
Integrated termination resistors
supporting 85
transmission
lines
PLL or bypass mode
Spread spectrum tolerable
1.05 to 3.3 V I/O supply voltage
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
Low phase jitter (Intel QPI, PCIe
Gen 1/2/3/4 common clock
compliant)
Gen 3 SRNS Compliant
100 ps input-to-output delay
Extended Temperature:
–40 to 85 °C
Package: 64-pin QFN
For higher output devices or
variations of this device, contact
Silicon Labs
Ordering Information:
See page 30.
Patents pending
Applications
Server
Storage
Data center
Enterprise Switches and Routers
Description
The Si53112-A03A is a low-power, 12-output, differential clock buffer that
meets all of the performance requirements of the Intel DB1200ZL
specification. To reduce board space and bill of material cost, the device
fully integrates all external resistors, supporting 85
transmission
lines.
The device is optimized for distributing reference clocks for Intel
®
QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4,
SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output has a dedicated hardware
output enable pin for maximum flexibility and power savings. Measuring
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter
Tool. Download it for free at
www.silabs.com/pcie-learningcenter.
Rev. 1.0 12/15
Copyright © 2015 by Silicon Laboratories
Si53112-A03A
Si53112-A03A
Functional Block Diagram
OE_[11:0]
12
FB_OUT
SSC Compatible
PLL
CLK_IN
CLK_IN
DIF_[11:0]
100M_133
HBW_BYPASS_LBW
SA_0
SA_1
PWRGD / PWRDN
SDA
SCL
Control
Logic
2
Rev. 1.0
Si53112-A03A
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. OE and Output Enables (Control Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5. PWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8. Buffer Power-Up State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Pin Descriptions: 64-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Rev. 1.0
3
Si53112-A03A
1. Electrical Specifications
Table 1. DC Operating Characteristics
V
DD_A
= 3.3 V±5%, V
DD
= 3.3 V±5%
Parameter
3.3 V Core Supply Voltage
3.3 V I/O Supply Voltage
1
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input Leakage Current
2
3.3 V Input High Voltage
3
3.3 V Input Low Voltage
3
3.3 V Input Low Voltage
3.3 V Input Med Voltage
3.3 V Input High Voltage
3.3 V Output High Voltage
4
3.3 V Output Low Voltage
4
Input Capacitance
5
Output Capacitance
5
Pin Inductance
Ambient Temperature
Symbol
VDD/VDD_A
VDD_IO
V
IH
V
IL
I
IL
V
IH_FS
V
IL_FS
V
IL_Tri
V
IM_Tri
V
IH_Tri
V
OH
V
OL
C
IN
C
OUT
L
PIN
T
A
Test Condition
3.3 V ±5%
1.05 V to 3.3 V ±5%
VDD
0 < VIN < VDD
VDD
Min
3.135
0.9975
2.0
VSS-0.3
–5
0.7
VSS–0.3
0
1.2
2.2
Max
3.465
3.465
VDD+0.3
0.8
+5
VDD+0.3
0.35
0.8
1.8
VDD
—
0.4
4.5
4.5
7
85
Unit
V
V
V
V
µA
V
V
V
V
V
V
V
pF
pF
nH
°C
I
OH
= –1 mA
I
OL
= 1 mA
2.4
—
2.5
2.5
—
No Airflow
–40
Notes:
1.
VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.
2.
Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state
current requirements.
3.
Internal voltage reference is to be used to guarantee V
IH
_FS and V
IL
_FS thresholds levels over full operating range.
4.
Signal edge is required to be monotonic when transitioning through this region.
5.
Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance.
4
Rev. 1.0
Si53112-A03A
Table 2. Current Consumption
T
A
= –40 to 85 °C; supply voltage V
DD
= 3.3 V ±5%
Parameter
Operating Current
Symbol
IDD
VDD
IDD
VDDA
IDD
VDDIO
Test Condition
133 MHz, VDD Rail, Zo=85
133 MHz, VDDA + VDDR, PLL Mode,
Zo=85
133 MHz, CL = Full Load, VDD IO
Rail, Zo=85
Power Down, VDD Rail
Power Down, VDDA Rail
Power Down, VDD_IO Rail
Min
—
—
—
—
—
—
Typ
18
17
85
0.4
2
0.2
Max
25
20
110
1
5
0.5
Unit
mA
mA
mA
mA
mA
mA
Power Down Current IDD
VDDPD
IDD
VDDAPD
IDD
VDDIOPD
Table 3. Output Skew, PLL Bandwidth and Peaking
T
A
= –40 to 85 °C; supply voltage V
DD
= 3.3 V ±5%
Parameter
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
DIF[11:0]
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Test Condition
Input-to-Output Delay in PLL Mode
Nominal Value
1,2,3,4
Input-to-Output Delay in Bypass Mode
\Nominal Value
2,4,5
Input-to-Output Delay Variation in PLL mode
Over voltage and temperature
2,4,5
Input-to-Output Delay Variation in Bypass Mode
Over voltage and temperature
2,4,5
Output-to-Output Skew across all 12 Outputs
(Common to Bypass and PLL Mode)
1,2,3,4,5
(HBW_BYPASS_LBW = 0)
6
(HBW_BYPASS_LBW = 1)
6
(HBW_BYPASS_LBW = 0)
7
(HBW_BYPASS_LBW = 1)
7
Min
–100
2.5
–100
–250
0
—
—
—
—
TYP
27
3.3
39
3.7
20
0.4
0.1
0.7
2
Max
100
4.5
100
250
50
2.0
2.5
1.4
4
Unit
ps
ns
ps
ps
ps
dB
dB
MHz
MHz
Notes:
1.
Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2.
Measured from differential cross-point to differential cross-point.
3.
This parameter is deterministic for a given device.
4.
Measured with scope averaging on to find mean value.
5.
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created
by it.
6.
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL
jitter peaking.
7.
Measured at 3 db down or half power point.
Rev. 1.0
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
