S i 5 2 11 2 - A 1 / A 2
PCI-E
XPRESS
G
EN
1
Features
DUAL
O
UTPUT
C
LOCK
G
ENERATOR
PCI-Express Gen 1 compliant
Low power HCSL differential
output buffers
Supports Serial-ATA (SATA) at
100 MHz
No termination resistors required
25 MHz Crystal Input or Clock
input
Triangular spread spectrum
profile for maximum EMI
reduction (Si52112-A2)
Extended Temperature:
–40 to 85 °C
3.3 V Power supply
Small package 10-pin TDFN
(3x3 mm)
Si52112-A1 does not support
spread spectrum outputs
Si52112-A2 supports 0.5% down
spread outputs
For PCIe Gen 2 applications, see
Si52112-B3/B4
For PCIe Gen 3 applications, see
Si52112-B5/B6
Ordering Information:
See page 13
Pin Assignments
Applications
Network Attached Storage
Multi-function Printer
Wireless Access Point
Routers
VDD
XOUT
XIN/CLKIN
VSS
1
2
3
4
5
10
9
8
7
6
VDD
DIFF2
DIFF2
DIFF1
DIFF1
Description
Si52112-A1/A2 is a high-performance, PCIe clock generator that can
source two PCIe clocks from a 25 MHz crystal or clock input. The clock
outputs are compliant to PCIe Gen 1 specifications. The ultra-small
footprint (3x3 mm) and industry leading low power consumption make
Si52112-A1/A2 the ideal clock solution for consumer and embedded
applications.
VDD
VSS
Patents pending
DIFF1
XIN/CLKIN
XOUT
PLL
Divider
DIFF2
VSS
Rev 1.2 7/14
Copyright © 2014 by Silicon Laboratories
Si52112-A1/A2
Si52112-A1/A2
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Crystal Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. Calculating Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1. 10-Pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. 8-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6.1. TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Rev 1.2
3
Si52112-A1/A2
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage (extended)
Supply Voltage (commercial)
Symbol
V
DD(extended)
V
DD(commercial)
Test Condition
3.3 V ± 5%
3.3 V ± 10%
Min
3.13
2.97
Typ
3.3
3.3
Max
3.46
3.63
Unit
V
V
Table 2. DC Electrical Specifications
Parameter
Operating Voltage
Operating Supply Current
Input Pin Capacitance
Output Pin Capacitance
Symbol
V
DD
I
DD
C
IN
C
OUT
Test Condition
3.3 V ± 10%
Full Active
Input Pin Capacitance
Output Pin Capacitance
Min
2.97
—
—
—
Typ
3.30
—
3
—
Max
3.63
17
5
5
Unit
V
mA
pF
pF
4
Rev 1.2
Si52112-A1/A2
Table 3. AC Electrical Specifications
Parameter
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CLKIN Rise and Fall Times
CLKIN Cycle-to-Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF Clocks
Duty Cycle
Symbol
L
ACC
T
DC
T
R
/T
F
T
CCJ
T
LTJ
V
IH
V
IL
I
IH
I
IL
T
DC
T
SKEW
F
OUT
F
ACC
t
r/f2
T
CCJ
Pk-Pk
GEN1
Test Condition
Measured at V
DD
/2 differential
Measured at V
DD
/2
Measured between 0.2 V
DD
and
0.8 V
DD
Measured at V
DD
/2
Measured at V
DD
/2
XIN/CLKIN pin
XIN/CLKIN pin
XIN/CLKIN pin, VIN = V
DD
XIN/CLKIN pin, 0 < VIN <0.8
Measured at 0 V differential
Measured at 0 V differential
VDD = 3.3 V
All output clocks
Min
—
45
0.5
—
—
2
—
—
–35
45
—
—
—
0.6
—
—
300
—
–0.3
Typ
—
—
—
—
—
—
—
—
—
—
—
100
Max
250
55
4.0
250
350
V
DD
+0.3
0.8
35
—
55
60
—
100
4.0
70
86
550
1.15
—
—
33
3
—
Unit
ppm
%
V/ns
ps
ps
V
V
uA
uA
%
ps
MHz
ppm
Skew
Output Frequency
Frequency Accuracy
Slew Rate
Cycle-to-Cycle Jitter
PCIe Gen 1 Pk-Pk Jitter
Crossing Point Voltage at 0.7 V
Swing
Voltage High
Voltage Low
Spread Range
Modulation Frequency
Enable/Disable and Set-up
Clock Stabilization from Power-
up
Stopclock Set-up Time
—
—
28
24
—
—
—
–0.5
31.5
—
—
Measured differentially from
±150 mV
Measured at 0 V differential
PCIe Gen 1
V/ns
ps
ps
mV
V
V
%
kHz
ms
ns
V
OX
V
HIGH
V
LOW
S
RNG
F
MOD
T
STABLE
T
SS
Down Spread, -A2 only
-A2 only
—
30
—
10.0
Note:
Visit
www.pcisig.com
for complete PCIe specifications.
Rev 1.2
5
FPGA/CPLD
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