MDB1900ZB
Zero Delay Buffer
for PCIe (Gen1/Gen2/Gen3),
SAS, SATA, ESI, and QPI
General Description
The MDB1900ZB is a true zero delay buffer with a fully-
integrated, high-performance, low-power, and low-phase
noise programmable PLL.
The MDB1900ZB is capable of distributing the reference
clocks for PCIe (Gen1/Gen2/Gen3), SATA, ESI, SAS, SMI
®
and
Intel Quickpath Interconnect (QPI).
The MDB1900ZB
works in conjunction with a CK410B+, CK509B or
CK420BQ clock synthesizer to provide reference clocks to
multiple agents.
The MDB1900ZB is designed for Intel’s DB1900Z
specification. The Intel part designation for the
MDB1900ZB is identified as G20746-002.
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
Features
•
Supports zero delay (0ps) buffer mode for 100MHz and
133MHz clock frequencies.
•
External feedback path for true zero delay operations
•
Zero delay (PLL) mode can filter jitter in incoming clock
•
Selectable PLL bandwidth for PLL mode
•
Supports fanout buffer mode for clock frequencies
between 0 and 250MHz
•
Differential input reference with HCSL logic (0~0.7V)
•
Nineteen differential HCSL-compatible clock output
pairs
•
Eight dedicated OE# pins to control their assigned
output. Glitch free assertion/de-assertion.
•
Spread spectrum modulation tolerant for EMI reduction
•
SMBus interface for controlling output properties
(enable/disable and delay tuning)
•
Disabled outputs in power-down mode for maximum
power savings
•
Nine selectable SMBus addresses so multiple devices
can share the same SMBus
•
3.3V or 2.5V operation
•
Commercial temperature range (0°C to +70°C)
•
72-pin 10mm × 10mm QFN package
•
GREEN, RoHS, and PFOS compliant
Block Diagram
Applications
•
PCI Express timing (Gen1/2/3) in Intel platforms,
specifically the Romley platform
•
SATA / SAS timing (storage)
•
ESI and SMI systems (storage)
•
Intel Quickpath Interconnect
Key Specifications
•
•
•
•
•
•
Intel is a registered trademark of Intel Corporation.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
Cycle-to-cycle jitter (PLL mode): <35ps
Output-to-output skew: <35ps
Input-to-output delay (PLL mode): Fixed at 0ps
Input-to-output delay variation (PLL mode): 13ps
Phase Jitter, PCIe Gen3: 0.25ps
Accumulated Jitter, QPI 9.6Gb/s: <0.15ps
September 3, 2015
Revision 1.2
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
MDB1900ZB
Ordering Information
Part Number
MDB1900ZBQY TR
MDB1900ZBQZ TR
Note:
1.
Device is GREEN, RoHS, and PFOS compliant. Lead finish is 100% matte tin.
Marking
MDB1900ZBQ
MDB1900ZBQ
Shipping
Tape and Reel
Tape and Reel
Ambient Temperature Range
-40°C to +85°C
0°C to +70°C
Package
(1)
72-Pin 10mm × 10mm QFN
72-Pin 10mm × 10mm QFN
Pin Configuration
72-Pin 10mm × 10mm QFN
September 3, 2015
2
Revision 1.2
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
MDB1900ZB
Pin Description
Pin Number
1
2
3
Pin Name
VDDA
GNDA
IREF
Type
(2)
Pin Function
3.3V or 2.5V Core Power Supply.
Core Ground.
I
REF
= (1.1V)/(R
IREF
). A precision resistor (R
IREF
) is attached to this pin and
to ground to set the reference current for the differential current mode
output pairs. R
IREF
= 475Ω for 100Ω trace, R
IREF
= 412Ω for 85Ω trace.
3.3V LVTTL Input. Input/output frequency select.
Logic 1 = 100MHz output (default, 50KΩ pull-up resistor)
Logic 0 = 133.33MHz output
Tri-level input for selecting bypass or PLL bandwidth mode.
High = High PLL bandwidth mode
Mid = Bypass mode
Low = Low PLL bandwidth mode
3.3V LVTTL Input for power good and power-down control. 50KΩ pull-down
resistor.
Ground.
3.3V or 2.5V power supply for differential clock input.
0.7V HCSL differential clock input reference. True input pin.
0.7V HCSL differential clock input reference. Complementary input pin.
Tri-level input to set SMBus address for this device. Works together with
SA_1.
Open Collector SMBus Data I/O Pin (SDATA). 5V tolerant.
SMBus Slave Clock Input (SCLK). 5V tolerant.
Tri-level input to set SMBus address for this device. Works together with
SA_0.
ZDB Feedback, 0.7V differential clock input, true input pin.
ZDB Feedback, 0.7V differential clock input, complementary input pin.
ZDB Feedback, 0.7V differential clock output (HCSL-compatible), true
output pin.
ZDB Feedback, 0.7V differential clock output (HCSL-compatible),
complementary output pin.
0.7V Differential Clock Output 0 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 0 (HCSL-compatible), complementary output
pin.
3.3V or 2.5V Power Supply.
0.7V Differential Clock Output 1 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 1 (HCSL-compatible), complementary output
pin.
0.7V Differential Clock Output 2 (HCSL-compatible), true output pin.
PWR
GND
I
4
100M_133M#
I, SE
5
HBW_BYPASS_LBW#
I, SE
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note:
2.
PWRGD/PWRDN#
GND
VDDR
CLK_IN
CLK_IN#
SA_0
SDA
SCL
SA_1
FB_IN
FB_IN#
FB_OUT
FB_OUT#
DIF_0
DIF_0#
VDD
DIF_1
DIF_1#
DIF_2
I, SE
GND
PWR
I, DIF
I, DIF
I, SE
I/O
I, SE
I, SE
I, DIF
I, DIF
O, DIF
O, DIF
O, DIF
O, DIF
PWR
O, DIF
O, DIF
O, DIF
I = Input
O = Output
I/O = Bi-directional
SE = Single-ended
DIF = Differential
PWR = 3.3V or 2.5V power
GND = Ground
September 3, 2015
3
Revision 1.2
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
MDB1900ZB
Pin Description (Continued)
Pin Number
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
DIF_2#
GND
DIF_3
DIF_3#
DIF_4
DIF_4#
VDD
DIF_5
DIF_5#
OE_5#
DIF_6
DIF_6#
OE_6#
DIF_7
DIF_7#
OE_7#
DIF_8
DIF_8#
OE_8#
GND
VDD
DIF_9
DIF_9#
OE_9#
DIF_10
DIF_10#
Type
(2)
Pin Function
0.7V Differential Clock Output 2 (HCSL-compatible), complementary output
pin.
Ground.
0.7V Differential Clock Output 3 (HCSL-compatible ), true output pin.
0.7V Differential Clock Output 3 (HCSL-compatible ), complementary output
pin.
0.7V Differential Clock Output 4 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 4 (HCSL-compatible), complementary output
pin.
3.3V or 2.5V power supply.
0.7V Differential Clock Output 5 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 5 (HCSL-compatible), complementary output
pin.
3.3V LVTTL active-low input for enabling Differential Output 5
(50kΩ pull-down).
0.7V Differential Clock Output 6 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 6 (HCSL-compatible), complementary output
pin.
3.3V LVTTL active-low input for enabling Differential Output 6
(50kΩ pull-down).
0.7V Differential Clock Output 7 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 7 (HCSL-compatible), complementary output
pin.
3.3V LVTTL active-low input for enabling Differential Output 7 (50kΩ pull-
down).
0.7V Differential Clock Output 8 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 8 (HCSL-compatible), complementary output
pin.
3.3V LVTTL active-low input for enabling Differential Output 8 (50kΩ pull-
down).
Ground
3.3V or 2.5V power supply.
0.7V Differential Clock Output 9 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 9 (HCSL-compatible), complementary output
pin.
3.3V LVTTL active-low input for enabling Differential Output 9
(50kΩ pull-down).
0.7V Differential Clock Output 10 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 10 (HCSL-compatible), complementary output
pin.
O, DIF
GND
O, DIF
O, DIF
O, DIF
O, DIF
PWR
O, DIF
O, DIF
I, SE
O, DIF
O, DIF
I, SE
O, DIF
O, DIF
I, SE
O, DIF
O, DIF
I, SE
GND
PWR
O, DIF
O, DIF
I, SE
O, DIF
O, DIF
September 3, 2015
4
Revision 1.2
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
MDB1900ZB
Pin Description (Continued)
Pin Number
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
ePad
Pin Name
OE_10#
DIF_11
DIF_11#
OE_11#
DIF_12
DIF_12#
OE_12#
VDD
DIF_13
DIF_13#
DIF_14
DIF_14#
GND
DIF_15
DIF_15#
DIF_16
DIF_16#
VDD
DIF_17
DIF_17#
DIF_18
DIF_18#
Exposed Pad
Type
(2)
Pin Function
3.3V LVTTL active-low input for enabling Differential Output 10
(50kΩ pull-down).
0.7V Differential Clock Output 11 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 11 (HCSL-compatible), complementary output
pin.
3.3V LVTTL active-low input for enabling Differential Output 11
(50kΩ pull-down).
0.7V Differential Clock Output 12 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 12 (HCSL-compatible), complementary output
pin.
3.3V LVTTL active-low input for enabling Differential Output 12 (50KΩ pull-
down).
3.3V or 2.5V Power Supply.
0.7V Differential Clock Output 13 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 13 (HCSL-compatible), complementary output
pin.
0.7V Differential Clock Output 14 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 14 (HCSL-compatible), complementary output
pin.
Ground.
0.7V Differential Clock Output 15 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 15 (HCSL-compatible), complementary output
pin.
0.7V Differential Clock Output 16 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 16 (HCSL-compatible), complementary output
pin.
3.3V or 2.5V Power Supply.
0.7V Differential Clock Output 17 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 17 (HCSL-compatible), complementary output
pin.
0.7V Differential Clock Output 18 (HCSL-compatible), true output pin.
0.7V Differential Clock Output 18 (HCSL-compatible), complementary output
pin.
The center pad must be connected to the ground plane both for electrical
ground and thermal relief.
I, SE
O, DIF
O, DIF
I, SE
O, DIF
O, DIF
I, SE
PWR
O, DIF
O, DIF
O, DIF
O, DIF
GND
O, DIF
O, DIF
O, DIF
O, DIF
PWR
O, DIF
O, DIF
O, DIF
O, DIF
GND
September 3, 2015
5
Revision 1.2
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or (408) 955-1690
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