S i 5 3 11
P
RELIMINARY
D
ATA
S
HEET
P
RECISION
H
IGH
S
PEED
C
LOCK
M
ULTIPLIER
/R
EGENERATOR
IC
Features
Complete precision high speed clock multiplier and regenerator device:
!
!
!
Performs Clock Multiplication to
One of Four Frequency Ranges:
150–167 MHz, 600–668 MHz,
1.2–1.33 GHz, or 2.4–2.67 GHz
Jitter Generation as low as
0.5 ps
RMS
for 622 MHz Output
Accepts Input Clock from
9.4–668 MHz
!
!
!
!
Regenerates a “Clean”, Jitter-
Attenuated Version of Input
Clock
DSPLL™ Technology Provides
Superior Jitter Performance
Small Footprint: 4 mm x 4 mm
Low Power: 310 mW typical
Ordering Information:
See page 22.
Applications
!
!
!
MULTOUT+
!
Description
The Si5311 is a fully integrated high-speed clock multiplier and clock
regenerator IC. The clock multiplier generates an output clock that is an
integer multiple of the input clock. When the clock multiplier is operating in
either the 150–167 MHz range or the 600–668 MHz range, the clock
regenerator operates simultaneously. The clock regenerator creates a
“clean” version of the input clock by using the clock synthesis phase-
locked loop (PLL) to remove unwanted jitter and square up the input
clock’s rising and falling edges. The Si5311 uses Silicon Laboratories
patented DSPLL
™
architecture to achieve superior jitter performance while
eliminating the analog loop filter found in traditional PLL designs.
The Si5311 represents a new standard in low jitter, small size, low power,
and ease-of-use for high speed clock devices. It operates from a single
2.5 V supply over the industrial temperature range (–40°C to 85°C).
REXT
VDD
GND
REFCLK+
REFCLK–
20 19 18
1
2
3
4
5
6
LOL
17 16
15
PWRDN/CAL
14
VDD
GND
Pad
MULTOUT–
MULTSEL1
MULTSEL0
SONET/SDH Systems
Terabit Routers
Digital Cross Connects
!
!
Optical Transceiver Modules
Gigabit Ethernet Systems
Hybrid VCO Modules
Pin Assignments
Si5311
GND
13
CLKOUT+
12
CLKOUT–
11
VDD
7
VDD
8
GND
9
CLKIN+
10
CLKIN–
Top View
Functional Block Diagram
R e ge ne ratio n
BUF
2
C L K O U T+
C L K O U T–
C a libra tion
2
C L K IN +
C L K IN –
BUF
D S P L L
TM
P h a se -L o cke d
Loop
P W R D N /C A L
BUF
2
M U L TO U T+
M U L TO U T –
LOL
2
2
B ia s G en
RE FCLK+
RE FCLK–
M U L TS E L1–0
REXT
Preliminary Rev. 0.6 6/01
Copyright © 2001 by Silicon Laboratories
Si5311-DS06
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5311
2
Preliminary Rev. 0.6
Si5311
T
A B L E O F
C
O N T E N T S
Section
Page
4
5
14
16
16
16
16
16
16
17
18
18
18
18
18
18
20
22
23
24
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1x Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSPLL Lock Detection (Loss-of-Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions: Si5311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.6
3
Si5311
Detailed Block Diagram
Regen
Retime
CLKOUT+
CLKOUT–
c
CLKIN+
CLKIN–
Phase
Detector
A/D
DSP
n
VCO
CLK
Divider
MULTOUT+
c
MULTOUT–
REFCLK+
REFCLK–
2
MULTSEL 1- 0 /
REXT
Bias
Generation
Lock
Detector
LOL
Calibration
PWRDN/CAL
Figure 1. Detailed Block Diagram
4
Preliminary Rev. 0.6
Si5311
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5311 Supply Voltage
2
Symbol
T
A
V
DD
Test Condition
Min
1
–40
2.375
Typ
25
2.5
Max
1
85
2.625
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.
2.
The Si5311 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of Figure 5 on page 13.
V
SIGNAL +
Differential
V
ICM
, V
O CM
SIGNAL –
I/Os
V
IS
(SIGNAL +) – (SIGNAL –)
Differential
Voltage Swing
V
ID
,V
O D
Differential Peak-to-Peak Voltage
t
Figure 2. Differential Voltage Measurement (CLKIN, REFCLK, CLKOUT, MULTOUT)
CLKIN
1/f
MULT
MULTOUT
t
CI-M
t
M-CO
CLKOUT
Figure 3. CLKIN to CLKOUT, MULTOUT Phase Relationship
CLKIN,
REFCLK,
CLKOUT,
MULTOUT
80%
20%
t
F
t
R
Figure 4. Clock Input and Output Rise/Fall Times
Preliminary Rev. 0.6
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
