nonvolatile, read/write storage solution for a wide
range of applications, having high programming
performance is achieved through highly-optimized
page buffer operations. Their symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and
memory cards. Their enhanced suspend
capabilities provide for an ideal solution for code +
data storage applications. For secure code storage
applications, such as networking, where code is
either directly executed out of flash or downloaded
to DRAM, the LH28F160S5-L/S5H-L offer three
levels of protection : absolute protection with V
PP
at
GND, selective hardware block locking, or flexible
software block locking. These alternatives give
designers ultimate control of their code security
needs. The LH28F160S5-L/S5H-L are conformed
to the flash Scalable Command Set (SCS) and the
Common Flash Interface (CFI) specification which
enable universal and upgradable interface, enable
the highest system/device data transfer rates and
minimize device and system-level implementation
costs.
16 M-bit (2 MB x 8/1 MB x 16) Smart 5
Flash Memories (Fast Programming)
• High performance read access time
LH28F160S5-L70
– 70 ns (5.0±0.25 V)/80 ns (5.0±0.5 V)
LH28F160S5H-L70
– 70 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)
LH28F160S5-L10/S5H-L10
– 100 ns (5.0±0.5 V)
• Enhanced automated suspend options
– Write suspend to read
– Block erase suspend to write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with V
PP
= GND
– Flexible block locking
– Erase/write lockout during power transitions
• SRAM-compatible write interface
• User-configurable x8 or x16 operation
• High-density symmetrically-blocked architecture
– Thirty-two 64 k-byte erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 3.2 million block erase cycles/chip
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I
CC
in static mode
• Automated write and erase
– Command user interface
– Status register
• ETOX
TM
∗
V nonvolatile flash technology
• Packages
– 56-pin TSOP Type I (TSOP056-P-1420)
Normal bend/Reverse bend
– 56-pin SSOP (SSOP056-P-0600)
5
[LH28F160S5-L]
– 64-ball CSP (FBGA064-P-0811)
– 64-pin SDIP (SDIP064-P-0750)
5
∗
ETOX is a trademark of Intel Corporation.
5
Under development
FEATURES
• Smart 5 technology
– 5 V V
CC
– 5 V V
PP
• High speed write performance
– Two 32-byte page buffers
– 2 µs/byte write transfer rate
• Common Flash Interface (CFI)
– Universal & upgradable interface
• Scalable Command Set (SCS)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
LH28F160S5-L/S5H-L
COMPARISON TABLE
VERSIONS
LH28F160S5-L70/L10
LH28F160S5H-L70/L10
OPERATING
TEMPERATURE
0 to +70˚C
– 40 to +85˚C
ACCESS TIME
DC CHARACTERISTICS
at 5.0±0.5 V V
CC
deep power-down current (MAX.)
80 ns/100 ns
90 ns/100 ns
15 µA
20 µA
PACKAGE
56-pin TSOP (I), 56-pin SSOP
5
,
64-ball CSP, 64-pin SDIP
5
56-pin TSOP (I), 64-ball CSP,
64-pin SDIP
5
5
Under development
PIN CONNECTIONS
56-PIN TSOP (Type I)
NC
CE
1
#
NC
A
20
A
19
A
18
A
17
A
16
V
CC
A
15
A
14
A
13
A
12
CE
0
#
V
PP
RP#
A
11
A
10
A
9
A
8
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
5
Under development
56-PIN SSOP
5
[LH28F160S5-L]
WP#
WE#
OE#
STS
DQ
15
DQ
7
DQ
14
DQ
6
GND
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
GND
DQ
11
DQ
3
DQ
10
DQ
2
V
CC
DQ
9
DQ
1
DQ
8
DQ
0
A
0
BYTE#
NC
NC
CE
0
#
A
12
A
13
A
14
A
15
NC
CE
1
#
NC
A
20
A
19
A
18
A
17
A
16
V
CC
GND
DQ
6
DQ
14
DQ
7
DQ
15
STS
OE#
WE#
WP#
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TOP VIEW
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
PP
RP#
A
11
A
10
A
9
A
1
A
2
A
3
A
4
A
5
A
6
A
7
GND
A
8
V
CC
DQ
9
DQ
1
DQ
8
DQ
0
A
0
BYTE#
NC
NC
DQ
2
DQ
10
DQ
3
DQ
11
GND
(TSOP056-P-1420)
(SSOP056-P-0600)
NOTE :
Reverse bend available on request.
-2-
LH28F160S5-L/S5H-L
PIN CONNECTIONS (contd.)
64-BALL CSP
1
A NC
B A
17
C A
15
D A
12
E
F
G
RP#
A
9
A
7
2
A
20
A
18
V
CC
CE
0
#
5
Under development
64-PIN SDIP
5
3
NC
A
19
A
14
A
13
A
11
A
10
A
5
A
3
4
NC
CE
1
#
TOP VIEW
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
5
WP#
WE#
DQ
6
NC
NC
DQ
9
NC
NC
6
OE#
DQ
15
DQ
5
DQ
12
DQ
3
DQ
10
DQ
0
BYTE#
7
STS
DQ
7
GND
V
CC
GND
V
CC
DQ
8
A
0
8
NC
DQ
14
DQ
13
DQ
4
DQ
11
DQ
2
DQ
1
NC
A
16
NC
NC
GND
A
2
A
1
V
PP
A
8
A
6
A
4
H NC
(FBGA064-P-0811)
V
PP
RP#
A
11
A
10
A
9
A
8
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
NC
NC
NC
NC
NC
NC
NC
BYTE#
A
0
DQ
0
DQ
8
DQ
1
DQ
9
V
CC
DQ
2
DQ
10
DQ
3
DQ
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CE
0
#
A
12
A
13
A
14
A
15
V
CC
A
16
A
17
A
18
A
19
A
20
NC
CE
1
#
NC
NC
NC
NC
WP#
WE#
OE#
STS
DQ
15
DQ
7
DQ
14
DQ
6
GND
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
GND
(SDIP064-P-0750)
-3-
LH28F160S5-L/S5H-L
BLOCK DIAGRAM
DQ
0
-DQ
15
OUTPUT
BUFFER
INPUT
BUFFER
QUERY
ROM
OUTPUT
MULTIPLEXER
I/O LOGIC
IDENTIFIER
REGISTER
DATA
REGISTER
PAGE
BUFFER
COMMAND
USER
INTERFACE
V
CC
BYTE#
CE#
WE#
OE#
RP#
WP#
STATUS
REGISTER
MULTIPLEXER
DATA
COMPARATOR
A
0
-A
20
INPUT
BUFFER
Y
DECODER
Y GATING
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
STS
V
PP
ADDRESS
LATCH
X
DECODER
32
64 k-BYTE
BLOCKS
V
CC
GND
ADDRESS
COUNTER
-4-
LH28F160S5-L/S5H-L
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
ADDRESS INPUTS :
Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
A
0 :
Byte Select Address. Not used in x16 mode (can be floated).
A
1
-A
4 :
Column Address. Selects 1 of 16-bit lines.
A
5
-A
15 :
Row Address. Selects 1 of 2 048-word lines.
A
16
-A
20
: Block Address.
DATA INPUT/OUTPUTS :
DQ
0
-DQ
7 :
Inputs data and commands during CUI write cycles; outputs data during
memory array, status register, query, and identifier code read cycles. Data pins float to
high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
DQ
8
-DQ
15 :
Inputs data during CUI write cycles in x16 mode; outputs data during memory
array read cycles in x16 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode (BYTE# = V
IL
). Data is internally latched during a write cycle.
CHIP ENABLE :
Activates the device’s control logic, input buffers decoders, and sense
amplifiers. Either CE
0
# or CE
1
# V
IH
deselects the device and reduces power
consumption to standby levels. Both CE
0
# and CE
1
# must be V
IL
to select the devices.
RESET/DEEP POWER-DOWN :
Puts the device in deep power-down mode and resets
internal automation. RP# V
IH
enables normal operation. When driven V
IL
, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE :
Gates the device’s outputs during a read cycle.
WRITE ENABLE :
Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#) :
Indicates the status of the internal WSM. When configured in level
mode (default mode), it acts as a RY/BY# pin. When low, the WSM is performing an
internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of
the STATUS pin, see the Configuration command (Table
3
and
Section 4.14).
WRITE PROTECT :
Master control for block locking. When V
IL
, locked blocks can not
be erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE :
BYTE# V
IL
places device in x8 mode. All data are then input or output
on DQ
0-7
, and DQ
8-15
float. BYTE# V
IH
places the device in x16 mode, and turns off the
A
0
input buffer.
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
BIT CONFIGURATION POWER SUPPLY :
For erasing array blocks, writing bytes or
configuring block lock-bits. With V
PP
≤
V
PPLK
, memory contents cannot be altered. Block
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an
invalid V
PP
(see
Section 6.2.3 "DC CHARACTERISTICS")
produce spurious results
and should not be attempted.
DEVICE POWER SUPPLY :
Internal detection configures the device for 5 V operation.
Do not float any power pins. With V
CC
≤
V
LKO
, all write attempts to the flash memory
are inhibited. Device operations at invalid V
CC
voltage (see
Section 6.2.3 "DC
CHARACTERISTICS")
produce spurious results and should not be attempted.
GROUND :
Do not float any ground pins.
NO CONNECT :
Lead is not internal connected; recommend to be floated.
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