Datasheet> 器件分类 > 可编程逻辑器件> 可编程逻辑> 5962-8867001LX

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5962-8867001LX: 产品描述OT PLD, 25ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24; 产品类别可编程逻辑器件可编程逻辑; 文件大小229KB，共12页; 制造商Cypress(赛普拉斯)

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5962-8867001LX概述

OT PLD, 25ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24

5962-8867001LX规格参数

参数名称	属性值
零件包装代码	DIP
包装说明	DIP,
针数	24
Reach Compliance Code	unknown
ECCN代码	3A001.A.2.C
其他特性	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS
最大时钟频率	30.3 MHz
JESD-30 代码	R-GDIP-T24
长度	31.877 mm
专用输入次数	11
I/O 线路数量	10
端子数量	24
最高工作温度	125 °C
最低工作温度	-55 °C
组织	11 DEDICATED INPUTS, 10 I/O
输出函数	MACROCELL
封装主体材料	CERAMIC, GLASS-SEALED
封装代码	DIP
封装形状	RECTANGULAR
封装形式	IN-LINE
可编程逻辑类型	OT PLD
传播延迟	25 ns
认证状态	Not Qualified
座面最大高度	5.08 mm
最大供电电压	5.5 V
最小供电电压	4.5 V
标称供电电压	5 V
表面贴装	NO
技术	CMOS
温度等级	MILITARY
端子形式	THROUGH-HOLE
端子节距	2.54 mm
端子位置	DUAL
宽度	7.62 mm
Base Number Matches	1

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For new designs, please refer to the PALCE22V10

PALC22V10D

Flash Erasable, Reprogrammable CMOS PAL® Device

Features

• Advanced second-generation PAL architecture

• Low power

— 90 mA max. commercial (10 ns)

— 130 mA max. commercial (7.5 ns)

• CMOS Flash EPROM technology for electrical erasabil-

ity and reprogrammability

• Variable product terms

— 2 x(8 through 16) product terms

• User-programmable macrocell

— Output polarity control

— Individually selectable for registered or combinato-

rial operation

• Up to 22 input terms and 10 outputs

• DIP, LCC, and PLCC available

— 7.5 ns commercial version

5 ns t

7.5 ns t

133-MHz state machine

— 10 ns military and industrial versions

6 ns t

10 ns t

110-MHz state machine

— 15-ns commercial and military

versions

— 25-ns commercial and military

versions

• High reliability

— Proven Flash EPROM technology

100% programming and functional testing

erased and reprogrammed. The programmable macrocell pro-

vides the capability of defining the architecture of each output

individually. Each of the 10 potential outputs may be specified

as “registered” or “combinatorial.” Polarity of each output may

also be individually selected, allowing complete flexibility of

output configuration. Further configurability is provided

through “array” configurable “output enable” for each potential

output. This feature allows the 10 outputs to be reconfigured

as inputs on an individual basis, or alternately used as a com-

bination I/O controlled by the programmable array.

PALC22V10D features a variable product term architecture.

There are 5 pairs of product term sums beginning at 8 product

terms per output and incrementing by 2 to 16 product terms

per output. By providing this variable structure, the PAL C

22V10D is optimized to the configurations found in a majority

of applications without creating devices that burden the prod-

uct term structures with unusable product terms and lower per-

formance.

Additional features of the Cypress PALC22V10D include a

synchronous preset and an asynchronous reset product term.

These product terms are common to all macrocells, eliminat-

ing the need to dedicate standard product terms for initializa-

tion functions. The device automatically resets upon power-up.

The PALC22V10D, featuring programmable macrocells and

variable product terms, provides a device with the flexibility to

implement logic functions in the 500- to 800-gate-array com-

plexity. Since each of the 10 output pins may be individually

configured as inputs on a temporary or permanent basis, func-

tions requiring up to 21 inputs and only a single output and

down to 12 inputs and 10 outputs are possible. The 10 poten-

tial outputs are enabled using product terms. Any output pin

may be permanently selected as an output or arbitrarily en-

abled as an output and an input through the selective use of

individual product terms associated with each output. Each of

these outputs is achieved through an individual programmable

macrocell. These macrocells are programmable to provide a

combinatorial or registered inverting or non-inverting output. In

a registered mode of operation, the output of the register is fed

back into the array, providing current status information to the

array. This information is available for establishing the next re-

sult in applications such as control state machines. In a com-

binatorial configuration, the combinatorial output or, if the out-

put is disabled, the signal present on the I/O pin is made

available to the array. The flexibility provided by both program-

mable product term control of the outputs and variable product

terms allows a significant gain in functional density through the

use of programmable logic.

Along with this increase in functional density, the Cypress

PALC22V10D provides lower-power operation through the use

of CMOS technology, and increased testability with Flash re-

programmability.

PAL is a registered trademark of Advanced Micro Devices

Functional Description

The Cypress PALC22V10D is a CMOS Flash Erasable sec-

ond-generation programmable array logic device. It is imple-

mented with the familiar sum-of-products (AND-OR) logic

structure and the programmable macrocell.

The PALC22V10D is executed in a 24-pin 300-mil molded DIP

a 300-mil cerDIP a 28-lead square ceramic leadless chip car-

rier, a 28-lead square plastic leaded chip carrier, and provides

up to 22 inputs and 10 outputs. The 22V10D can be electrically

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134 •

408-943-2600

July 1991 - Revised October 1995

5962-8867001LX相似产品对比

	5962-8867001LX	5962-8753901LX	5962-88670013X	5962-8867002LX
描述	OT PLD, 25ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24	UV PLD, 25ns, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24	OT PLD, 25ns, CMOS, CQCC28, CERAMIC, LCC-28	OT PLD, 30ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
零件包装代码	DIP	DIP	QLCC	DIP
包装说明	DIP,	WDIP,	QCCN,	DIP,
针数	24	24	28	24
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN代码	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
其他特性	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS
最大时钟频率	30.3 MHz	30.3 MHz	30.3 MHz	25 MHz
JESD-30 代码	R-GDIP-T24	R-GDIP-T24	S-CQCC-N28	R-GDIP-T24
长度	31.877 mm	31.877 mm	11.43 mm	31.877 mm
专用输入次数	11	11	11	11
I/O 线路数量	10	10	10	10
端子数量	24	24	28	24
最高工作温度	125 °C	125 °C	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C
组织	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O
输出函数	MACROCELL	MACROCELL	MACROCELL	MACROCELL
封装主体材料	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED
封装代码	DIP	WDIP	QCCN	DIP
封装形状	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR
封装形式	IN-LINE	IN-LINE, WINDOW	CHIP CARRIER	IN-LINE
可编程逻辑类型	OT PLD	UV PLD	OT PLD	OT PLD
传播延迟	25 ns	25 ns	25 ns	30 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	5.08 mm	5.08 mm	1.9812 mm	5.08 mm
最大供电电压	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压	5 V	5 V	5 V	5 V
表面贴装	NO	NO	YES	NO
技术	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY	MILITARY
端子形式	THROUGH-HOLE	THROUGH-HOLE	NO LEAD	THROUGH-HOLE
端子节距	2.54 mm	2.54 mm	1.27 mm	2.54 mm
端子位置	DUAL	DUAL	QUAD	DUAL
宽度	7.62 mm	7.62 mm	11.43 mm	7.62 mm
Base Number Matches	1	1	1	1

5962-8867001LX

5962-8867001LX概述

5962-8867001LX规格参数

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5962-8867001LX相似产品对比

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