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TMC2242C
Digital Half-Band Interpolating/Decimating Filter
12-bit In/16-bit Out, 60 MHz
Features
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Pin-compatible upgrade of TMC2242B
User-selectable interpolate d.c. gain, 0 dB or -6 dB
True unity d.c. gain in all “0 db” modes
40 MSPS performance in equal-rate filter modes
40 and 60 MSPS speed grades in all other modes
User-selectable 2:1 decimation, 1:2 interpolation, and
equal-rate filter modes, plus unfiltered bypass/delay mode
Defeatable
π
x/sin(
π
x) compensation filter
Passband ripple <0.014 dB
Stopband rejection >56 dB
Dedicated 12-bit two’s complement or unsigned input bus
16-bit two’s complement or unsigned output bus with
user-selectable rounding to 8 to 16 effective bits
Programmable limiter prevents overflow or clips to
CCIR601 levels
New double-latency modes match Y channel data flow to
slower-sampled C
B
and C
R
data flows
New dual-channel interpolation and decimation for
YUV422
Description
The TMC2242C, a linear-phase low-pass half-band digital
filter with fixed coefficients, can be used to halve or double
the sampling rate of a digital signal. When used as a decimat-
ing post-filter with a double-speed oversampling A/D con-
verter, it greatly reduces the cost and complexity of the
required analog antialiasing pre-filters. When used as an
interpolating pre-filter with a double-speed oversampling
D/A converter, it greatly reduces the complexity and cost of
the necessary analog post-filter, particularly when its x/sin(x)
correction filter is engaged.
The TMC2242C user selects the mode of operation (deci-
mate, interpolate, equal-rate, bypass, x/sin(x))and rounding.
The part can accept 12-bit two’s complement or unsigned
data at up to 60 MHz and can output saturated two’s comple-
ment or offset binary data rounded to from 8 to 16 bits.
Within the speed grade I/O limit, the output sample rate may
be 1/2, 1, or 2 times the input sample rate. Two-channel
modes permit it to interpolate or to decimate two multi-
plexed data streams (such as video C
B
and C
R
) jointly.
The filter response is flat to within
±
0.014 dB up to 0.21f
s
(e.g. 5.75MHz at a 27MHz clock rate), with stopband attenu-
ation greater than 56dB above 0.29f
s
. Symmetric-coefficient
filters such as the TMC2242C always have linear phase
response. Half-band response is -6 dB.
Fabricated on an advanced submicron CMOS process, the
TMC2242C is available in a 44-lead PLCC package. Perfor-
mance is guaranteed from 0 to 70
°
C and over a power supply
range of 4.75 to 5.25V.
Applications
• Digital-to-Analog Converter Prefiltering with optional
x/sinx correction
• 1:2 interpolation
• Analog-to-Digital Converter Postfiltering
• 2:1 decimation
• Low-ripple low-pass (0 to 0.2 f
s
) filter
Block Diagram
SI
11-0
ZERO
INSERT
FIR
FILT
X/SIN(X)
FILTER
ROUND
LIMIT
DECIMATE
SO
15-0
SO
3-0
CONTROL
65-2242C-01
DEC
INT
SYNC TCO RND
OE
Rev. 1.0.0
PRODUCT SPECIFICATION
TMC2242C
Functional Description
The TMC2242C implements a fixed-coefficient linear-phase
Finite Impulse Response (FIR) filter, with special rate-
matching input and output structures for decimation and
interpolation. For parts of each speed grade, the faster of
either the input or the output bus will operate at the respec-
tive guaranteed maximum clock rate. The total internal
pipeline latency from the input of an impulse to the corre-
sponding output peak (digital group delay) is 34 clock
cycles; the 39-value output response begins after 15 clock
cycles and ends after 53 cycles. (The double-latency interpo-
lation and decimation modes feature group delays of 68
clock cycles.)
To interpolate, the chip accepts incoming data on alternate
clock cycles, inserting zeroes on the remaining clock cycles.
In decimation mode, the chip’s output register is strobed at
half the clock rate. In bypass and equal-rate filter modes,
these input zero insertion and output register hold functions
are disabled.
When interpolating, the user should normally bring SYNC
HIGH for at least one clock cycle, returning it LOW with the
first desired input data value. The chip will then continue to
accept data on alternate rising edges of CLK. The user may
leave SYNC LOW or change its value once per clock cycle,
with equivalent results. The chip can be powered up and
operated with SYNC grounded, but the input-to-output
latency may vary by 1/2 input sample period and the host
system won’t know which (even- or odd-numbered) CLK
rising edges strobe the input register. The setup and hold tim-
ing requirements for SYNC, with respect to the rising edges
of CLK, are the same as those for all other data and control
inputs except OE, which is asynchronous. In two-channel
mode, it must remain low after the first incoming data value.
When decimating, the user should likewise bring SYNC
HIGH for at least one clock cycle, returning it LOW when a
fresh output is desired. The chip will continue to update the
output register on alternate rising edges of CLK. The user
may leave SYNC LOW or change its value once per clock
cycle, with equivalent results. The chip can be powered up
and operated with SYNC grounded, but the host system
won’t know whether the data outputs are updated on even- or
odd-numbered system clock cycles. In any half-band deci-
mating filter, a given single-cycle impulse’s arrival time (on
an odd versus an even clock cycle) determines whether it
generates a half-amplitude two-cycle impulse or a half-
speed, 40-clock, filtered output shaped by the nonzero, non-
center coefficients. The SYNC control permits the host sys-
tem to obtain consistent results. In two-channel mode, it
must remain low after the first incoming data value.
When the result is rounded to fewer than 16 bits, the
unneeded lowest positions of the output bus are tristated
and become supplementary control bits, which enable the
x/sin(x) filter, bypass/delay, double-latency, dual-channel,
and other special modes. Unless more than 12 output bits are
enabled, the TMC2242C offers x/sin(x) correction filtering,
with or without the main low-pass filter, and without impact-
ing the 34-cycle group delay. Bidirectional pins SO
3-2
enable these modes, per Table 1. If 14 or more output bits are
used, the low pass filter remains enabled, the x/sin(x),
disabled.
Table 1. Operating Modes
INT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DEC RND
2
SO
3-2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Output
Output
Output
Output
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
Function
Interpolate (0 dB)
Interpolate
1
(-6 dB)
Decimate
Equal Rate Lowpass
Interpolate (0 dB)
Interpolate
1
(-6 dB)
Decimate
Equal Rate Lowpass
Interpolate (0 dB)
* x/sinx
Interpolate
1
(-6 dB)
* x/sinx
Decimate * x/sinx
Equal Rate LPF * x/sinx
Delay + Interpolate
2
(0 dB)
Delay + Interpolate
2
(0 dB) * x/sinx
Delay + Decimate
2
Bypass (Delay Only)
2-Channel Interpolate
3
(0 db)
2-Channel Interpolate
3
* x/sinx
2-Channel Decimate
3
Delay * x/sinx
Note:
1. These modes limit to 15 bits (SO
14-0
) instead of 16
(SO
15-0
) and are provided for backward compatibility to
earlier parts.
2. These modes, which double the chip’s overall group delay
from 34 to 68 CLK cycles, can be used to equalize inter-
component delays where Y is sampled at twice the rate of
C
B
or C
R
(e.g. 4:2:2 and 8:4:4 formats).
3. These modes accommodate multiplexed two-channel da-
ta, e.g. C
B/
C
R
.
2
TMC2242C
PRODUCT SPECIFICATION
Table 2. Package Interconnections
Signal
Type
Timing
Data In
Name
CLK
SYNC
SI
11-0
Function
Clock
Synchronization
Input Data Port
PLCC
Pin
42
43
40,
37-30,
27-25
4-11,
14-17
18-21
44
1
22-24
2
3
MQFP
Pin
36
37
34,
31-24,
21-19
42-44,
1-5,
8-11
12-15
38
39
16-18
40
41
The output data format is two’s complement if TCO is HIGH,
inverted or offset binary if LOW. Unless all 16 output bits are
used, the user can also select either signed or unsigned input
data, via pin SO
0
(see pin description note 2, below). As
shown in pin description note 1, the output is half-LSB
rounded to the resolution selected by the value of RND
2-0
.
The asynchronous three-state output enable control simplifies
connection to a data bus with other drivers.
Data Out SO
15-4
Output Data Port
Dual-
SO
3-0
Function
Controls
INT
DEC
RND
2-0
TCO
OE
Output
Data; Controls
Interpolate
Decimate
Rounding
Position
Output Format
Output Enable
Pin Assignments
SO
13
SO
14
SO
15
OE
TCO
DEC
INT
SYNC
CLK
GND
SI
11
SO
13
SO
14
SO
15
OE
TCO
DEC
INT
SYNC
CLK
GND
SI
11
44
43
42
41
40
39
38
37
36
35
44
43
42
41
40
6
5
4
3
2
1
18
19
20
21
22
23
24
25
26
27
28
SO
12
SO
11
SO
10
SO
9
SO
8
GND
V
DD
SO
7
SO
6
SO
5
SO
4
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
TMC2242C
GND
V
DD
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
V
DD
12
13
14
15
16
17
18
19
20
21
SO
3
SO
2
SO
1
SO
0
RND
2
RND
1
RND
0
SI
0
SI
1
SI
2
GND
65-2242C-02A
65-2242C-02B
44 Lead PLCC
SO
3
SO
2
SO
1
SO
0
RND
2
RND
1
RND
0
SI
0
SI
1
SI
2
GND
44 Lead MQFP
22
SO
12
SO
11
SO
10
SO
9
SO
8
GND
V
DD
SO
7
SO
6
SO
5
SO
4
34
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
TMC2242C
GND
V
DD
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
V
DD
3
PRODUCT SPECIFICATION
TMC2242C
Pin Descriptions
Pin Number
Pin Name
CLK
PLCC
42
MQFP
36
Pin Function Description
Clock
. The chip operates from a single-phase master clock, to whose rising
edges all timing parameters are referenced. All internal registers are strobed on
every rising edge of CLK, although the output register is strobed on alternate
rising edges during decimation. In all modes, the frequency applied to CLK is the
higher of the input and output data sampling rates. During interpolation, the chip
reads its input bus on alternate rising edges of CLK.
Synchronization
. During interpolation, the chip accepts input data on alternate
rising edges of CLK and inserts zeroes on the remaining cycles. If SYNC is
HIGH during CLK rising edge 0 and LOW during CLK rising edge 1, the chip will
accept data on CLK 1 and insert a zero on CLK 2. Thereafter, if SYNC is either
held LOW or fed a square wave of half the CLK frequency, the part will continue
to accept data on odd-numbered CLK edges and to stuff zeroes on even-
numbered edges. Similarly, during decimation, the output data change only on
alternate clock cycles. If the user operates SYNC as above, each even-
numbered rising edge of CLK will trigger a change in the output. In all other
modes, the state of SYNC doesn’t affect operation of the chip.
Input Data
. A 12-bit two’s complement or unsigned input word is registered by
the rising edges of CLK. SI
0
is the LSB.
Dedicated Timing Controls
SYNC
43
37
Dedicated Data Input Port
SI
11-0
40,
37-30,
27-25
4-11,
14-21
34,
31-24,
21-19
42-44,
1-5,
8-15
Dedicated Data Output Port
SO
15-0
Output Data MSBs
. When OE is LOW, the 12 most significant bits of the filter’s
output emerge here, following each rising edge of CLK. The format may be two’s
complement, unsigned, or inverted offset binary. Bits SO
15-4
correspond to
input bits SI
11-0
, respectively. An on-chip limiter prevents overflows and
underflows in the output data.
Output Data
. These pins serve as data outputs when RND
2
is LOW. When
RND
2
is HIGH, they become additional filter mode controls (Table 1).
Output Data 2
nd
LSB.
This pin is a data output when RND
2-1
are LOW. When
either RND
2
or RND
1
is HIGH, it becomes an additional rounding control.
1
Output Data LSB
. This pin is a data output if and only if all RND bits are LOW.
Otherwise, it augments the data I/O format controls.
2
44, 1
2
38, 39
40
Interpolate and Decimate.
Jointly with SO
3-2
, these bits select the chip’s
overall operating mode, as discussed earlier in Table 1
Output format control.
When TCO is HIGH, the output data are in two’s
complement format. When TCO is LOW, they are inverted offset binary, unless
SO
0
is HIGH and RND is nonzero, in which case they are unsigned.
Round and output tristate.
Selects output rounding position and active bus
width 8-16 bits. All outputs at and below the rounding bit position are tristated,
allowing the 4 LSBs to become control inputs.
Output enable.
LOW activates output bus from SO
15
down to the effective LSB,
as chosen by RND
2-0
. All drivers at and below the rounding point are disabled,
as are all drivers when OE is HIGH.
Dual Function Data Output/Control Input Pins
SO
3-2
SO
1
SO
0
Dedicated Static Controls (Set state before first desired data input.)
INT, DEC
TCO
RND
2-0
22-24
16-18
Active, Asynchronous Control
OE
3
41
4
PRODUCT SPECIFICATION
TMC2242C
Notes:
1. Rounding Operation Detail
RND
2-0
000
001
010
011
100
100
101
110
111
SO
1
Output
A
Output
A
X
X
0
1
0
1
X
Output Rounding
SO
15-0
(16 bits)
SO
15-1
(15 bits)
SO
15-2
(14 bits)
SO
15-3
(13)
SO
15-4
(12)
SO
15-8
(8)
SO
15-5
(11)
SO
15-6
(10)
SO
15-7
(9)
2. I/O Format Operation Detail
RND
0
0
>0
>0
>0
>0
SO
0
Output
Output
0
0
1
1
TCO
0
1
0
1
0
1
In Format
2’s Comp
2’s Comp
2’s Comp
2’s Comp
Unsigned
Unsigned
Out Format
Inverted
Offset
2’s Comp
Inverted
Offset
2’s Comp
Unsigned
2’s Comp
A. If RND
2-0
= 00X, do not drive SO
1
, externally.
Absolute Maximum Ratings
(beyond which the device may be damaged)
1
Parameter
Supply Voltage
Input Voltage
Output Applied Voltage
2
Externally Forced Current
3,4
Short Circuit Duration
Operating Temperature (Case)
Junction Temperature
Lead Soldering Temperature
Storage Temperature
10 seconds
-65
Single output in HIGH state to ground
-20
Conditions
Min
-0.5
-0.5
-0.5
-3.0
Max
7.0
V
DD
+ 0.5
V
DD
+ 0.5
+6.0
1
110
140
300
150
Units
V
V
V
mA
sec
°C
°C
°C
°C
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating
Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
5
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