电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

R1QAA3618CBG-22RT

产品描述QDR SRAM
产品类别存储    存储   
文件大小301KB,共38页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 全文预览

R1QAA3618CBG-22RT概述

QDR SRAM

R1QAA3618CBG-22RT规格参数

参数名称属性值
Objectid1292990275
包装说明LBGA,
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
YTEOL6.75
最长访问时间0.45 ns
JESD-30 代码R-PBGA-B165
长度17 mm
内存密度37748736 bit
内存集成电路类型QDR SRAM
内存宽度18
功能数量1
端子数量165
字数2097152 words
字数代码2000000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织2MX18
封装主体材料PLASTIC/EPOXY
封装代码LBGA
封装形状RECTANGULAR
封装形式GRID ARRAY, LOW PROFILE
并行/串行PARALLEL
座面最大高度1.4 mm
最大供电电压 (Vsup)1.9 V
最小供电电压 (Vsup)1.7 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子形式BALL
端子节距1 mm
端子位置BOTTOM
宽度15 mm

文档预览

下载PDF文档
hinT=00000.0000.0000.0000.0000
--
-
00000.1100
.
1100
.
0000
.
0000---
00000.0000.0000.0000.0000---QDRII+_RL25
R1QAA36**CB* / R1QDA36**CB* Series
R1QAA3636CBG / R1QAA3618CBG
/ R1QAA3609CBG
R1QDA3636CBG / R1QDA3618CBG
/ R1QDA3609CBG
R1QGA3636CBG / R1QGA3618CBG / R1QGA3609CBG
R1QKA3636CBG / R1QKA3618CBG / R1QKA3609CBG
36-Mbit QDR™II+ SRAM
4-word Burst
Description
The R1Q#A3636 is a 1,048,576-word by 36-bit and the R1Q#A3618 is a 2,097,152-word by 18-bit synchronous
quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory
cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled
by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable
for applications which require synchronous operation, high speed, low voltage, high density and wide bit
configuration. These products are packaged in 165-pin plastic FBGA package.
#
= A: Read Latency =2.5, w/o ODT
#
= D: Read Latency =2.5, w/ ODT
# = G: Read Latency =2.0, w/o ODT
# = K: Read Latency =2.0, w/ ODT
R10DS0158EJ0009
Rev. 0.09a
2011.09.14
Features
Power Supply
• 1.8 V for core (V
DD
), 1.4 V to V
DD
for I/O (V
DDQ
)
Clock
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with s restart
I/O
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR read and write operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Data valid pin (QVLD) to indicate valid data on the output
Function
• Four-tick burst for reduced address frequency
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
Package
• 165 FBGA package (15 x 17 x 1.4 mm)
Notes:
1.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)
2. The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics Sales Office regarding specifications.
3. Refer to
"http://www.renesas.com/products/memory/fast_sram/qdr_sram/qdr_sram_root.jsp"
for the latest and detailed information.
4. Descriptions about x9 parts in this datasheet are just for reference.
Rev. 0.09a : 2011.09.14
R10DS0158EJ0009
PAGE : 1

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2809  1614  1009  1560  2367  57  33  21  32  48 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved