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EQRD23L2L-155.520M

产品描述LVPECL, Quartz Crystal Clock Oscillators XO (SPXO) LVPECL (PECL) 3.3Vdc 6 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) Quartz Crystal Clock Oscillators XO (SPXO) LVPECL (PECL) 3.3Vdc 6 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)
产品类别无源元件    振荡器   
文件大小1MB,共12页
制造商ECLIPTEK
官网地址http://www.ecliptek.com
标准  
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EQRD23L2L-155.520M概述

LVPECL, Quartz Crystal Clock Oscillators XO (SPXO) LVPECL (PECL) 3.3Vdc 6 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) Quartz Crystal Clock Oscillators XO (SPXO) LVPECL (PECL) 3.3Vdc 6 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)

EQRD23L2L-155.520M规格参数

参数名称属性值
Brand NameEcliptek
是否无铅不含铅
是否Rohs认证符合
Objectid7042828852
零件包装代码SMD 3.2mm x 5.0mm
针数6
制造商包装代码SMD 3.2mm x 5.0mm
Reach Compliance Codecompliant
其他特性STANDBY; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; BULK; TAPE
最长下降时间0.4 ns
频率调整-机械NO
频率稳定性25%
JESD-609代码e4
安装特点SURFACE MOUNT
标称工作频率155.52 MHz
最高工作温度85 °C
最低工作温度-40 °C
振荡器类型LVPECL
输出负载50 OHM
物理尺寸5.0mm x 3.2mm x 1.2mm
最长上升时间0.4 ns
最大供电电压3.465 V
最小供电电压3.135 V
标称供电电压3.3 V
表面贴装YES
最大对称度55/45 %
端子面层Nickel/Gold (Ni/Au)

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Ecliptek | EQRD23 Series Oscillator
http://www.ecliptek.com/oscillators/EQRD23/
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EQRD23 Series Oscillator
Quartz Crystal Clock Oscillators XO (SPXO) LVPECL (PECL) 3.3Vdc 6 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)
2011/65 +
2015/863
168 SVHC
Revision C 06/11/2014
Electrical Specifications
Nominal Frequency
20.000MHz to 200.000MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability
Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency
Stability over the Operating Temperature Range, Supply Voltage
Change, Output Load Change, First Year Aging at 25°C, Shock, and
Vibration
±100ppm Maximum
±50ppm Maximum
±25ppm Maximum
±20ppm Maximum
0°C to +70°C
-20°C to +70°C
-40°C to +85°C
±3ppm Maximum First Year
3.3V
DC
±5%
50mA Maximum
V
DD
-1.025V
DC
Minimum, 2.35V
DC
Typical, V
DD
-0.88V
DC
Maximum
V
DD
-1.81V
DC
Minimum, 1.60V
DC
Typical, V
DD
-1.62V
DC
Maximum
Measured at 50% of waveform
50 ±10(%)
50 ±5(%)
Measured at 20% to 80% of Waveform
400pSec Maximum
50 Ohms into V
DD
-2.0V
DC
LVPECL
Click to Open Phase Noise Table
Standby (on Pad 1)
Standby (on Pad 2)
70% of V
DD
Minimum or No Connect to Enable Output and
Complementary Output
30% of V
DD
Maximum to Disable Output and Complementary Output
(High Impedance)
10mSec Maximum
200nSec Maximum
Operating Temperature Range
Aging at 25°C
Supply Voltage
Input Current
Output Voltage Logic High (V
OH
)
Output Voltage Logic Low (V
OL
)
Duty Cycle
Rise Time/Fall Time
Load Drive Capability
Output Logic Type
Phase Noise
Output Control Function
Output Control Input Voltage Logic High
(Vih)
Output Control Input Voltage Logic Low
(Vil)
Standby Output Enable Time
Standby Output Disable Time
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28-Jan-2016 2:19 PM

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