INTEGRATED CIRCUITS
DATA SHEET
SAA7108AE; SAA7109AE
HD-CODEC
Product specification
Supersedes data of 2003 Mar 26
2004 Jun 29
Philips Semiconductors
Product specification
HD-CODEC
CONTENTS
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
9
9.1
9.2
9.3
9.4
9.5
9.6
FEATURES
Video decoder
Video scaler
Video encoder
Common features
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAMS
PINNING
FUNCTIONAL DESCRIPTION OF DIGITAL
VIDEO ENCODER PART
Reset conditions
Input formatter
RGB LUT
Cursor insertion
RGB Y-C
B
-C
R
matrix
Horizontal scaler
Vertical scaler and anti-flicker filter
FIFO
Border generator
Oscillator and Discrete Time Oscillator (DTO)
Low-pass Clock Generation Circuit (CGC)
Encoder
RGB processor
Triple DAC
HD data path
Timing generator
Pattern generator for HD sync pulses
I
2
C-bus interface
Power-down modes
Programming the graphics acquisition scaler of
the video encoder
Input levels and formats
FUNCTIONAL DESCRIPTION OF DIGITAL
VIDEO DECODER PART
Decoder
Decoder output formatter
Scaler
VBI data decoder and capture
(subaddresses 40H to 7FH)
Image port output formatter
(subaddresses 84H to 87H)
Audio clock generation
(subaddresses 30H to 3FH)
10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
11
11.1
11.2
12
13
14
15
16
16.1
16.2
17
17.1
17.2
17.3
18
18.1
18.2
19
19.1
19.2
19.3
19.4
20
21
22
23
24
25
SAA7108AE; SAA7109AE
INPUT/OUTPUT INTERFACES AND PORTS
OF DIGITAL VIDEO DECODER PART
Analog terminals
Audio clock signals
Clock and real-time synchronization signals
Video expansion port (X port)
Image port (I port)
Host port for 16-bit extension of video data I/O
(H port)
Basic input and output timing diagrams for the
I and X ports
BOUNDARY SCAN TEST
Initialization of boundary scan circuit
Device identification codes
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS OF THE DIGITAL
VIDEO ENCODER PART
CHARACTERISTICS OF THE DIGITAL
VIDEO DECODER PART
TIMING
Digital video encoder part
Digital video decoder part
APPLICATION INFORMATION
Reconstruction filter
Analog output voltages
Suggestions for a board layout
I
2
C-BUS DESCRIPTION
Digital video encoder part
Digital video decoder part
PROGRAMMING START SET-UP OF
DIGITAL VIDEO DECODER PART
Decoder part
Audio clock generation part
Data slicer and data type control part
Scaler and interfaces
PACKAGE OUTLINE
SOLDERING
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2004 Jun 29
2
Philips Semiconductors
Product specification
HD-CODEC
1
1.1
FEATURES
Video decoder
SAA7108AE; SAA7109AE
•
Six analog inputs, internal analog source selectors, e.g.
6
×
CVBS or (2
×
Y/C and 2
×
CVBS) or (1
×
Y/C and
4
×
CVBS)
•
Two analog preprocessing channels in differential
CMOS style for best S/N performance
•
Fully programmable static gain or Automatic Gain
Control (AGC) for the selected CVBS or Y/C channel
•
Switchable white peak control
•
Two built-in analog anti-aliasing filters
•
Two 9-bit video CMOS Analog-to-Digital Converters
(ADCs), digitized CVBS or Y/C signals are available on
the Image Port Data (IPD) port under I
2
C-bus control
•
On-chip clock generator
•
Line-locked system clock frequencies
•
Digital PLL for horizontal sync processing and clock
generation, horizontal and vertical sync detection
•
Requires only one crystal (either 24.576 MHz or
32.11 MHz) for all standards
•
Automatic detection of 50 and 60 Hz field frequency,
and automatic switching between PAL and NTSC
standards
•
Luminance and chrominance signal processing for
PAL BGHI, PAL N, combination PAL N, PAL M,
NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and
SECAM
•
User programmable luminance peaking or aperture
correction
•
Cross-colour reduction for NTSC by chrominance comb
filtering
•
PAL delay line for correcting PAL phase errors
•
Brightness Contrast Saturation (BCS) and hue control
on-chip
•
Two multi functional real-time output pins controlled by
the I
2
C-bus
•
Multi-standard VBI data slicer decoding World Standard
Teletext (WST), North-American Broadcast Text
System (NABTS), Closed Caption (CC), Wide Screen
Signalling (WSS), Video Programming System (VPS),
Vertical Interval Time Code (VITC) variants
(EBU/SMPTE) etc.
•
Standard ITU 656 Y-C
B
-C
R
4 : 2 : 2 format (8-bit) on IPD
output bus
(1) Macrovision™ is a trademark of the Macrovision Corporation.
•
Enhanced ITU 656 output format on IPD output bus
containing:
– active video
– raw CVBS data for INTERCAST applications
(27 MHz data rate)
– decoded VBI data
•
Detection of copy protected input signals according to
the Macrovision™
(1)
standard. Can be used to prevent
unauthorized recording of pay-TV or video tape signals.
1.2
Video scaler
•
Both up and downscaling
•
Conversion to square pixel format
•
NTSC to 288 lines (video phone)
•
Phase accuracy better than
1
/
64
pixel or line, horizontally
or vertically
•
Independent scaling definitions for odd and even fields
•
Anti-alias filter for horizontal scaling
•
Provides output as:
– scaled active video
– raw CVBS data for INTERCAST, WAVE-PHORE,
POPCON applications or general VBI data decoding
(27 MHz or sample rate converted)
•
Local video output for Y-C
B
-C
R
4 : 2 : 2 format (VMI,
VIP, ZV).
2004 Jun 29
3
Philips Semiconductors
Product specification
HD-CODEC
1.3
Video encoder
SAA7108AE; SAA7109AE
•
Adjustable output levels for the DACs
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
Internal Colour Bar Generator (CBG)
•
Optional support of various Vertical Blanking Interval
(VBI) data insertion
•
Macrovision Pay-per-View copy protection system
rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option;
this applies to SAA7108AE only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.
1.4
Common features
•
Digital PAL/NTSC encoder with integrated high quality
scaler and anti-flicker filter for TV output from a PC
•
Supports Intel® Digital Video Out (DVO) low voltage
interfacing to graphics controller
•
27 MHz crystal-stable subcarrier generation
•
Maximum graphics pixel clock 85 MHz at double edged
clocking, synthesized on-chip or from external source
•
Programmable assignment of clock edge to bytes (in
double edged mode)
•
Synthesizable pixel clock (PIXCLK) with minimized
output jitter, can be used as reference clock for the VGC,
as well
•
PIXCLK output and bi-phase PIXCLK input (VGC clock
loop-through possible)
•
Hot-plug detection through dedicated interrupt pin
•
Supported VGA resolutions for PAL or NTSC legacy
video output up to 1280
×
1024 graphics data at
60 or 50 Hz frame rate
•
Supported VGA resolutions for HDTV output up to
1920
×
1080 interlaced graphics data at 60 or 50 Hz
frame rate
•
Three Digital-to-Analog Converters (DACs) for CVBS
(BLUE, C
B
), VBS (GREEN, CVBS) and C (RED, C
R
) at
27 MHz sample rate (signals in parenthesis are
optionally selected), all at 10-bit resolution
•
Non-interlaced C
B
-Y-C
R
or RGB input at maximum
4 : 4 : 4 sampling
•
Downscaling and upscaling from 50 to 400 %
•
Optional interlaced C
B
-Y-C
R
input of Digital Versatile
Disk (DVD) signals
•
Optional non-interlaced RGB output to drive second
VGA monitor (bypass mode, maximum 85 MHz)
•
3
×
256 bytes RGB Look-Up Table (LUT)
•
Support for hardware cursor
•
HDTV up to 1920
×
1080 interlaced and 1280
×
720
progressive, including 3-level sync pulses
•
Programmable border colour of underscan area
•
Programmable 5 line anti-flicker filter
•
On-chip 27 MHz crystal oscillator (3rd-harmonic or
fundamental 27 MHz crystal)
•
Fast I
2
C-bus control port (400 kHz)
•
Encoder can be master or slave
•
5 V tolerant digital I/O ports
•
I
2
C-bus controlled (full read-back ability by an external
controller, bit rate up to 400 kbits/s)
•
Versatile power-save modes
•
Boundary scan test circuit complies with the
“IEEE Std.
1149.b1-1994”
(separate ID codes for decoder and
encoder)
•
Monolithic CMOS 3.3 V device
•
BGA156 package
•
Moisture Sensitive Level (MSL): e3.
2
APPLICATIONS
•
Notebook (low-power consumption)
•
PCMCIA card application
•
AGP based graphics cards
•
PC editing
•
Image processing
•
Video phone applications
•
INTERCAST and PC teletext applications
•
Security applications
•
Hybrid satellite set-top boxes.
2004 Jun 29
4
Philips Semiconductors
Product specification
HD-CODEC
3
GENERAL DESCRIPTION
SAA7108AE; SAA7109AE
All inputs intended to interface to the host graphics
controller are designed for low-voltage signals down to
1.1 V and up to 3.45 V.
The
video decoder,
a 9-bit video input processor, is a
combination of a 2-channel analog pre-processing circuit
including source selection, anti-aliasing filter and
Analog-to-Digital Converter (ADC), automatic clamp and
gain control, a Clock Generation Circuit (CGC), and a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
combination PAL N, NTSC M, NTSC-Japan, NTSC N,
NTSC 4.43 and SECAM).
The decoder includes a brightness, contrast and
saturation control circuit, a multi-standard VBI data slicer
and a 27 MHz VBI data bypass. The pure 3.3 V (5 V
compatible) CMOS circuit SAA7108AE; SAA7109AE,
consisting of an analog front-end and digital video
decoder, a digital video encoder and analog back-end, is a
highly integrated circuit especially designed for desktop
video applications.
The decoder is based on the principle of line-locked clock
decoding and is able to decode the colour of PAL, SECAM
and NTSC signals into ITU-R BT.601 compatible colour
component values.
The encoder can operate fully independently at its own
variable pixel clock, transporting graphics input data, and
at the line-locked, single crystal-stable video encoding
clock.
As an option, it is possible to slave the video PAL/NTSC
encoding to the video decoder clock with the encoder FIFO
acting as a buffer to decouple the line-locked decoder
clock from the crystal-stable encoder clock.
The SAA7108AE; SAA7109AE is a new multi-standard
video decoder and encoder chip, offering high quality
video input and TV output processing as required by
PC-99 specifications. It enables hardware manufacturers
to implement versatile video functions on a significantly
reduced printed-circuit board area at very competitive
costs.
Separate pins for supply voltages as well as for I
2
C-bus
control and boundary scan test have been provided for the
video encoder and decoder sections to ensure both
flexible handling and optimized noise behaviour.
The
video encoder
is used to encode PC graphics data at
maximum 1280
×
1024 resolution (optionally 1920
×
1080
interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals.
A programmable scaler and anti-flicker filter (maximum
5 lines) ensures properly sized and flicker-free TV display
as CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters
(DACs) can output RGB signals together with a TTL
composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA
monitor can be connected to the RGB outputs and
separate H and V-syncs as well, thereby serving as an
auxiliary monitor at maximum 1280
×
1024
resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this
port can provide Y, P
B
and P
R
signals for HDTV monitors.
The encoder section includes a sync/clock generator and
on-chip DACs.
4
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
BGA156
DESCRIPTION
plastic ball grid array package; 156 balls; body 15
×
15
×
1.15 mm
VERSION
SOT472-1
SAA7108AE
SAA7109AE
2004 Jun 29
5
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