ADVANCED INFORMATION
MX29L1611G
16M-BIT [2M x 8/1M x 16] CMOS
SINGLE VOLTAGE FLASH EEPROM
FEATURES
•
•
•
•
•
3.3V
±
10% for write and read operation
11V Vpp erase/programming operation
Endurance: 100 cycles
Fast random access time: 90ns/120ns
Sector erase architecture
- 32 equal sectors of 64k bytes each
- Sector erase time: 200ms typical
• Auto Erase and Auto Program Algorithms
- Automatically erases any one of the sectors or the
whole chip
- Automatically programs and verifies data at specified
addresses
• Status Register feature for detection of program or
erase cycle completion
• Low VCC write inhibit is equal to or less than 1.8V
• Software data protection
• Page program operation
- Internal address and data latches for 64 words per
page
- Page programming time: 5ms typical
• Low power dissipation
- 50mA active current
- 20uA standby current
• Two independently Protected sectors
• Package type
- 42 pin plastic DIP
GENERAL DESCRIPTION
The MX29L1611G is a 16-mega bit Flash memory
organized as either 1M wordx16 or 2M bytex8. The
MX29L1611G includes 32 sectors of 64KB(65,536 Bytes
or 32,768 words). MXIC's Flash memories offer the most
cost-effective and reliable read/write non-volatile random
access memory. The MX29L1611G is packaged in 42
pin PDIP.
The standard MX29L1611G offers access times as fast
as 100ns,allowing operation of high-speed
microprocessors without wait. To eliminate bus contention,
the MX29L1611G has separate chip enable CE and,
output enable (OE).
MXIC's Flash memories augment EPROM functionality
with electrical erasure and programming. The
MX29L1611G uses a command register to manage this
functionality.
MX29L1611G does require high input voltages for
programming. Commands require 11V input to determine
the operation of the device. Reading data out of the
device is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 100 cycles. The MXIC's cell is designed to
optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29L1611G uses a 11V Vpp supply to perform the
Auto Erase and Auto Program algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
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MX29L1611G
Table1.PIN DESCRIPTIONS
SYMBOL
A0 - A19
Q0 - Q7
TYPE
INPUT
INPUT/OUTPUT
NAME AND FUNCTION
ADDRESS INPUTS: for memory addresses. Addresses are internally latched
during a write cycle.
LOW-BYTE DATA BUS: Input data and commands during Command Interface
Register(CIR) write cycles. Outputs array,status and identifier data in the
appropriate read mode. Floated when the chip is de-selected or the outputs are
disabled.
Q8 - Q14
INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations.
Outputs array, identifier data in the appropriate read mode; not used for status
register reads. Floated when the chip is de-selected or the outputs are disabled
Q15/A -1
CE
INPUT/OUTPUT
INPUT
Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB
ADDRESS(BYTE = LOW) for raed operation.
CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,
decoders and sense amplifiers. With CE high, the device is deselected and
power consumption reduces to Standby level upon completion of any current
program or erase operations. CE must be low to select the device.
OUTPUT ENABLES: Gates the device's data through the output buffers during
a read cycle OE is active low.
BYTE ENABLE: While operating read mode, BYTE Low places device in x8
mode. All data is then input or output on Q0-7 and Q8-14 float. AddressQ15/
A-1 selects between the high and low byte. While operating read mode, BYTE
high places the device in x16 mode, and turns off the Q15/A-1 input buffer.
Address A0, then becomes the lowest order address.
ERASE/PROGRAM ENABLE:When BYTE/VPP=11V would place this device
into ERASE/PROGRAM mode.
DEVICE POWER SUPPLY(3.3V
±
10%)
GROUND
OE
BYTE/VPP
INPUT
INPUT
VCC
GND
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MX29L1611G
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Table 2.1 Bus Operations for Word-Wide Mode (BYTE/VPP = VIH)
Mode
Read
Output Disable
Standby
Manufacturer ID
Device ID
Write
Notes
1
1
1
2,4
2,4
1,3,5
CE
VIL
VIL
VIH
VIL
VIL
VIL
OE
VIL
VIH
X
VIL
VIL
VIH
BYTE/VPP A0
VIH
VIH
H/L
VIH
VIH
VPP
X
X
X
VIL
VIH
X
A1
X
X
X
VIL
VIL
X
A9
X
X
X
VID
VID
X
Q0-Q7
DOUT
High Z
High Z
C2H
F6H
DIN
Q8-Q14 Q15/A-1
DOUT
High Z
HIgh Z
00H
00H
DIN
DOUT
HighZ
HighZ
0B
0B
DIN
Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)
Mode
Read
Output Disable
Standby
Manufacturer ID
Device ID
Write
Notes
1
1
1
2,4
2,4
1,3,5
CE
VIL
VIL
VIH
VIL
VIL
VIL
OE
VIL
VIH
X
VIL
VIL
VIH
BYTE/VPP
VIL
VIL
H/L
VIL
VIL
VPP
A0
X
X
X
VIL
VIH
X
A1
X
X
X
VIL
VIL
X
A9
X
X
X
VID
VID
X
Q0-Q7
DOUT
High Z
High Z
C2H
F6H
DIN
Q8-Q14
HighZ
High Z
HIgh Z
High Z
High Z
DIN
Q15/A-1
VIL/VIH
X
X
VIL
VIL
DIN
NOTES :
1. X can be VIH or VIL for address or control pins.
2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and
with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4),A2~A19=Do not care.
3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully
completed through proper command sequence.
4. VID = 11.5V- 12.5V
5.Word mode only for write operation VPP=10.5V~11.5V
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