HIGH-SPEED 8/4K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
◆
◆
IDT709359/49L
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
– Industrial: 7.5ns (max.)
Low-power operation
– IDT709359/49L
Active: 925mW (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the
FT/PIPE
pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
◆
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83 MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) package
and a 100-pin fine pitch Ball Grid Array (fpBGA)
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/
W
R
UB
R
CE
0R
CE
1L
LB
L
OE
L
1
0
0/1
1
0
0/1
CE
1R
LB
R
OE
R
FT
/PIPE
L
0/1
1b 0b
b a
1a 0a
0a 1a
a
b
0b 1b
0/1
FT
/PIPE
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
I/O
Control
I/O
9R
-I/O
17R
I/O
Control
I/O
0R
-I/O
8R
A
12L
(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
A
12R
(1)
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
5633 drw 01
NOTE:
1. A
12
is a NC for IDT709349.
AUGUST 2003
1
©2003 Integrated Device Technology, Inc.
DSC-5633/2
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
The IDT709359/49 is a high-speed 8/4K x 18 bit synchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
Description
With an input data register, the IDT709359/49 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by
CE
0
and CE
1,
permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 925mW of power.
Pin Configurations
(1,2,3,4)
06/28/02
Index
A
9L
A
10L
A
11L
A
12L
(1)
NC
NC
NC
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
V
CC
FT/PIPE
L
I/O
17L
I/O
16L
GND
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CNTEN
L
CLK
L
ADS
L
GND
GND
ADS
R
CLK
R
CNTEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
709359/49PF
PN100-1
(5)
100-Pin TQFP
Top View
(6)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
8R
A
9R
A
10R
A
11R
A
12R
(1)
NC
NC
NC
LB
R
UB
R
CE
0R
CE
1R
CNTRST
R
R/W
R
GND
OE
R
FT/PIPE
R
I/O
17R
GND
I/O
16R
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
.
5633 drw 02
NOTES:
1. A
12
is a NC for IDT709349.
2. All V
CC
pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
V
CC
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
V
CC
I/O
7R
I/O
8R
I/O
9R
I/O
10R
2
6.42
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations (con't.)
(1,2,3,4)
709359/49BF
BF100
(5)
100-Pin fpBGA
Top View
(6)
A2
A3
A4
CNTRST
R
06/28/02
A1
A5
A6
A7
A8
A9
A10
A
8R
B1
A
11R
B2
UB
R
B3
GND GND
GND I/O
13R
I/O
10R
I/O
17R
A
6R
C1
A
7R
C2
A
10R
C3
B6
B7
B9
B4
B5
B10
B8
(1)
A
12R
R/W
R
OE
R
PL/FT
R
I/O
12R
I/O
9R
I/O
6R
C4
C5
C6
C7
C8
C9
C10
A
3R
D1
A
4R
D2
A
5R
D3
A
9R
D4
CE
1R
I/O
16R
I/O
15R
I/O
11R
I/O
7R
I/O
3R
D5
D6
D7
D8
D9
D10
A
0R
E1
CLK
R
E2
A
1R
E3
CNTEN
R
F3
A
2R
E4
LB
R
E5
CE
0R
I/O
14R
I/O
8R
I/O
5R
I/O
1R
E6
E7
E8
E9
E10
GND
ADS
R
F1
F2
A
1L
F4
ADS
L
F5
GND I/O
4R
F6
F7
I/O
2R
I/O
0R
F8
F9
V
CC
F10
GND CLK
L
G1
CNTEN
L
H1
G2
A
0L
G3
A
3L
G4
V
CC
G5
GND
G6
V
CC
G7
I/O
2L
G8
I/O
1L
G9
I/O
0L
G10
A
4L
H2
A
7L
H3
UB
L
H4
GND I/O
13L
H5
CNTRST
L
NC
H7
I/O
4L
H8
GND I/O
3L
H9
H10
,
H6
A
2L
J1
A
6L
J2
A
11L
J3
CE
0L
J4
I/O
15L
I/O
9L
I/O
7L
J6
J7
J8
I/O
6L
J9
I/O
5L
J10
J5
A
5L
K1
A
9L
K2
A
12L
K3
(1)
R/W
L
K4
OE
L
PL/FT
L
I/O
12L
I/O
10L
GND
K5
K6
K7
K8
K9
I/O
8L
K10
A
8L
A
10L
LB
L
CE
1L
V
CC
V
CC
I/O
16L
I/O
14L
I/O
11L
I/O
17L
5633 drw 03
NOTES:
1. A
12
is a NC for IDT709349.
2. All V
CC
pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
12L
(1)
I/O
0L
- I/O
17L
CLK
L
UB
L
LB
L
ADS
L
CNTEN
L
CNTRST
L
FT/PIPE
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
12R
(1)
I/O
0R
- I/O
17R
CLK
R
UB
R
LB
R
ADS
R
CNTEN
R
CNTRST
R
FT/PIPE
R
V
CC
GND
Names
Chip Enables
(3)
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Upper Byte Select
(2)
Lower Byte Select
(2)
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (5V)
Ground (0V)
5633 tbl 01
NOTES:
1. A
12
is a NC for IDT709349.
2.
LB
and
UB
are single buffered regardless of state of
FT/PIPE.
3.
CEo
and CE
1
are single buffered when
FT/PIPE
= V
IL
,
CEo
and CE
1
are double buffered when
FT/PIPE
= V
IH
,
i.e. the signals take two cycles to deselect.
Truth Table I—Read/Write and Enable Control
(1,2,3)
OE
X
X
X
X
X
X
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE
0
(5)
H
X
L
L
L
L
L
L
L
L
CE
1
(5)
X
L
H
H
H
H
H
H
H
H
UB
(4)
X
X
H
L
H
L
L
H
L
X
LB
(4)
X
X
H
H
L
L
H
L
L
X
R/W
X
X
X
L
L
L
H
H
H
X
Upper Byte
I/O
9-17
High-Z
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
Lower B
yte
I/O
0-8
High-Z
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected—Power Down
Deselected—Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
5633 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signa
4.
LB
and
UB
are single buffered regardless of state of
FT/PIPE.
5.
CEo
and CE
1
are single buffered when
FT/PIPE
= V
IL
.
CEo
and CE
1
are double buffered when
FT/PIPE
= V
IH
, i.e. the signals take two cycles to deselect.
4
6.42
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control
(1,2)
External
Address
An
X
X
X
Previous
Internal
Address
X
An
An + 1
X
Internal
Address
Used
An
An + 1
An + 1
A
0
CLK
↑
↑
↑
↑
ADS
L
(4)
H
H
X
CNTEN
X
L
(5)
H
X
CNTRST
H
H
H
L
(4)
I/O
(3)
D
I/O
(n)
D
I/O
(n+1)
D
I/O
(n+1)
D
I/O
(0)
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disab led (An + 1 reused)
Counter Reset to Address 0
5633 tbl 03
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
,
LB, UB,
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
CNTRST
are independent of all other signals including
CE
0
, CE
1
,
UB
and
LB.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
, CE
1
,
UB
and
LB.
.
Recommended Operating
Recommended DC Operating
Temperature and Supply Voltage
(1)
Conditions
Grade
Commercial
Industrial
Ambient
Temperature
(1)
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
5633 tbl 04
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(2)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(1)
0.8
Unit
V
V
V
V
5633 tbl 05
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. V
TERM
must not exceed V
cc
+ 10%.
2. V
IL
> -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Capacitance
(1)
Symbol
C
IN
C
OUT
(3)
Parameter
Input Capacitance
(T
A
= +25°C, f = 1.0MH
z
)
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
5633 tbl 07
Output Capacitance
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
o
mA
5633 tbl 06
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
cc
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+ 10%.
6.42
5
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
