SiT5356
1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3,
Elite Platform™ Precision Super-TCXO
Description
The
SiT5356
is a ±100 ppb precision MEMS Super-TCXO
that is fully compliant to Telcordia GR-1244-CORE Stratum
3 oscillator specifications. Engineered for best dynamic
performance, the SiT5356 is ideal for high reliability
telecom, wireless and networking, industrial, precision
GNSS and audio/video applications.
Leveraging SiTime’s unique DualMEMS™ temperature
sensing and TurboCompensation™ technologies, the
SiT5356 delivers the best dynamic performance for timing
stability in the presence of environmental stressors such as
air flow, temperature perturbation, vibration, shock, and
electromagnetic interference. This device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for a dedicated external LDO.
The SiT5356 offers three device configurations that can be
ordered using
Ordering Codes
for:
Features
◼
◼
◼
◼
◼
◼
◼
◼
◼
◼
◼
◼
Any frequency from 1 MHz to 60 MHz in 1 Hz steps
Factory programmable options for short lead time
Best dynamic stability under airflow, thermal shock
▪
±100 ppb stability across temperature
▪
±1 ppb/C typical frequency slope (ΔF/ΔT)
▪
1.5e-11 ADEV at 10 second averaging time
-40°C to +105°C operating temperature
No activity dips or micro jumps
Resistant to shock, vibration and board bending
On-chip regulators eliminate the need for external LDOs
Digital frequency pulling (DCTCXO) via I
2
C
▪
Digital control of output frequency and pull range
▪
Up to
±3200
ppm pull range
▪
Frequency pull resolution down to 5 ppt
2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
LVCMOS or clipped sinewave output
RoHS and REACH compliant
Pb-free, Halogen-free, Antimony-free
Applications
◼
◼
◼
The SiT5356 can be factory programmed for any
combination of frequency, stability, voltage, and pull range.
Programmability enables designers to optimize clock
configurations while eliminating long lead times and
customization costs associated with quartz devices where
each frequency is custom built.
Refer to
Manufacturing Guideline
for proper reflow profile
and PCB cleaning recommendations to ensure best
performance.
◼
◼
◼
◼
◼
◼
4G/5G radio, Small cell
IEEE1588 boundary and grandmaster clocks
Carrier-grade routers and switches
Synchronous Ethernet
Optical transport – SONET/SDH, OTN, Stratum 3
DOCSIS 3.x remote PHY
GPS disciplined oscillators
Precision GNSS systems
Test and measurement
Block Diagram
5.0 mm x 3.2 mm Package Pinout
SDA / NC
OE / VC / NC
SCL / NC
NC
GND
1
10
9
VDD
NC
NC
CLK
2
3
8
7
4
5
6
A0 / NC
Figure 1. SiT5356 Block Diagram
Figure 2. Pin Assignments (Top view)
(Refer to
Table 13
for Pin Descriptions)
Rev 1.07
May 10, 2020
www.sitime.com
SiT5356
1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Ordering Information
The part number guide illustrated below is for reference only, in which boxes identify order codes having more than one option.
To customize and build an exact part number, use the SiTime
Part Number Generator.
To validate the part number, use the
SiTime
Part Number Decoder.
Part
Family
Silicon
Revision
Letter
Package Size
"F": 5.0 mm x 3.2 mm
Pin 1 Function
–
TCXO mode only
"E": Output Enable
"N": No Connect
TCXO
VCTCXO
DCTCXO
Temperature Range
SiT5356AC - FQ - 33 E 0 -
19.123456
T
SiT5356AC - FQ - 33 V T -
19.123456
T
SiT5356AC - FQG33 J R -
19.123456
T
Packaging
"T": 12 mm Tape & Reel, 3 ku reel
"Y": 12 mm Tape & Reel, 1 ku reel
"X": 12 mm Tape & Reel, 250 u reel
(blank): bulk
[2]
"I": Industrial, -40 to 85°C
"C": Extended Commercial, -20 to 70°C
"E": Extended Industrial, -40 to 105°C
Output Waveform
"-": LVCMOS
[1]
"C": Clipped Sinewave
Frequency
1.000000 MHz to 60.000000 MHz
Frequency Stability
"Q": for
±0.1
ppm
"P": for
±0.2
ppm
"N": for
±0.25
ppm
Pull Range
–
DCTCXO mode only
"T":
±6.25
ppm
"R":
±10
ppm
"Q":
±12.5
ppm
"M":
±25
ppm
"B":
±50
ppm
"C":
±80
ppm
"E":
±100
ppm
"F":
±125
ppm
"G":
"H":
"X":
"L":
"Y":
"S":
"Z":
"U":
±150 ppm
±200 ppm
±400 ppm
±600 ppm
±800 ppm
±1200 ppm
±1600 ppm
±3200 ppm
I
2
C Address Mode
–
DCTCXO mode only
“0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “A”, “B”,
“C”, “D”, “E”, “F”: Order code representing hex
value of I
2
C address. When the I
2
C address is
factory programmed using this code, pin A0 is no
connect (NC).
“G”: I
2
C pin addressable mode. Address is set by
the logic on A0 pin.
Pin 1 Function
–
DCTCXO mode only
"I": Output Enable
"J": No Connect, software OE control
Supply Voltage
"25": 2.5 V
±10%
"28": 2.8 V
±10%
"30": 3.0 V
±10%
"33": 3.3 V
±10%
Notes:
1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in
Table 1
(Electrical Characteristics). Contact
SiTime
for other rise/fall time
options for best EMI or driving multiple loads. For differential outputs, contact
SiTime.
2. Bulk is available for sampling only.
Rev 1.07
Page 2 of 41
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SiT5356
1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics.............................................................................................................................................................. 4
Device Configurations and Pin-outs ........................................................................................................................................... 10
Pin-out Top Views............................................................................................................................................................... 10
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 11
Waveforms................................................................................................................................................................................. 13
Timing Diagrams ........................................................................................................................................................................ 14
Stability Diagrams ...................................................................................................................................................................... 14
Typical Performance Plots ......................................................................................................................................................... 15
Architecture Overview ................................................................................................................................................................ 19
Frequency Stability ............................................................................................................................................................. 19
Output Frequency and Format ............................................................................................................................................ 19
Output Frequency Tuning ................................................................................................................................................... 19
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 20
Device Configurations ................................................................................................................................................................ 20
TCXO Configuration ........................................................................................................................................................... 20
VCTCXO Configuration ...................................................................................................................................................... 21
DCTCXO Configuration ...................................................................................................................................................... 22
VCTCXO-Specific Design Considerations ................................................................................................................................. 23
Linearity .............................................................................................................................................................................. 23
Control Voltage Bandwidth ................................................................................................................................................. 23
FV Characteristic Slope K
V
................................................................................................................................................. 23
Pull Range, Absolute Pull Range ........................................................................................................................................ 24
DCTCXO-Specific Design Considerations ................................................................................................................................. 25
Pull Range and Absolute Pull Range .................................................................................................................................. 25
Output Frequency ............................................................................................................................................................... 26
I
2
C Control Registers .......................................................................................................................................................... 28
Register Descriptions.......................................................................................................................................................... 28
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 28
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 29
Register Address: 0x02. DIGITAL PULL RANGE CONTROL
[18]
........................................................................................ 30
Serial Interface Configuration Description .......................................................................................................................... 31
Serial Signal Format ........................................................................................................................................................... 31
Parallel Signal Format ........................................................................................................................................................ 32
Parallel Data Format ........................................................................................................................................................... 32
I
2
C Timing Specification ...................................................................................................................................................... 34
I
2
C Device Address Modes ................................................................................................................................................. 35
Schematic Example ............................................................................................................................................................ 36
Dimensions and Patterns ........................................................................................................................................................... 37
Layout Guidelines ...................................................................................................................................................................... 38
Manufacturing Guidelines .......................................................................................................................................................... 38
Additional Information ................................................................................................................................................................ 39
Revision History ......................................................................................................................................................................... 40
Rev 1.07
Page 3 of 41
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SiT5356
1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3 V Vdd.
Table 1. Output Characteristics
Parameters
Nominal Output Frequency Range
Operating Temperature Range
Symbol
F_nom
T_use
Min.
1
-20
-40
-40
Frequency Stability over
Temperature
Initial Tolerance
Supply Voltage Sensitivity
Output Load Sensitivity
Frequency vs. Temperature Slope
F_stab
–
Typ.
–
–
–
–
–
Max.
60
+70
+85
+105
±0.1
Unit
MHz
°C
°C
°C
ppm
Extended Commercial, ambient temperature
Industrial, ambient temperature
Extended Industrial, ambient temperature
Referenced to (max frequency + min frequency)/2 over the
rated temperature range, in TCXO, DCTCXO, or VCTCXO
(VCTCXO with ±6.25 ppm pull range, Vc=Vdd/2)
Initial frequency at 25°C at 48 hours after 2 reflows
Vdd ±5%
LVCMOS output, 15 pF ±10%. Clipped sinewave output,
10 kΩ || 10 pF ±10%
0.5°C/min temperature ramp rate, -20 to 85°C
0.5°C/min temperature ramp rate, -40 to -20°C
0.5°C/min temperature ramp rate, 85 to 105°C
0.5°C/min temperature ramp rate, -20 to 85°C
0.5°C/min temperature ramp rate, -40 to -20°C
0.5°C/min temperature ramp rate, 85 to 105°C
Inclusive of frequency variation due to temperature,
±10%
supply variation,
±1.5
pF load variation and 24-hour aging
-40 to 105°C, 0.5°C/min ramp rate, defined as
±ΔF/2
as
shown in
Figure 19,
contact
SiTime
for lower hysteresis
-40 to 85°C, 0.5°C/min ramp rate, defined as
±ΔF/2
as
shown in
Figure 19,
contact
SiTime
for lower hysteresis
-20 to 70°C, 0.5°C/min ramp rate, defined as
±ΔF/2
as
shown in
Figure 19,
contact
SiTime
for lower hysteresis
At 85°C, after 30-days of continued operation. Aging is
measured with respect to day 31.
At 85°C, after 2-days of continued operation. Aging is
measured with respect to day 3.
Condition
Frequency Coverage
Temperature Range
Frequency Stability
–
Stratum 3+ Grade
F_init
F_Vdd
F_load
ΔF/ΔT
–
–
–
–
–
–
–
±0.5
±0.05
±0.9
±1
±0.9
±0.008
±0.01
±0.008
–
±25
±15
±10
±0.5
±57
±73
±80
±87
1.5e-11
–
–
–
±3.0
±0.3
±6.4
±0.05
–
±3
±1
±2
–
±0.3
±2.5
±0.4
±2
±3.5
±3.3
±0.02
±0.03
±0.028
±0.15
±42
±27
±20
±2.0
±230
±320
±360
±400
–
±0.2
±0.25
±1
±6.5
±1.1
±10
±0.08
±0.28
±5
–
–
±4.6
ppm
ppb
ppb
ppb/°C
ppb/°C
ppb/°C
ppb/s
ppb/s
ppb/s
ppm
ppb
ppb
ppb
ppb
ppb
ppb
ppb
ppb
–
ppm
ppm
ppm
ppb
ppb
ppb/°C
ppb/s
ppm
ppb
ppm
ppm
ppm
Dynamic Frequency Change during
Temperature Ramp
F_dynamic
–
–
–
24-hour holdover stability
Hysteresis Over Temperature
F_24_Hold
F_hys
–
–
–
–
One-Day Aging
One-Year Aging
5-Year Aging
10-Year Aging
20-Year Aging
Allan deviation
Frequency Stability over
Temperature
Initial Tolerance
Supply Voltage Sensitivity
Output Load Sensitivity
Frequency vs. Temperature Slope
Dynamic Frequency Change during
Temperature Ramp
24-hour holdover stability
One-Day Aging
One-Year Aging
20-Year Aging
20-Year Total Stability
F_1d
F_1y
F_5y
F_10y
F_20y
ADEV
F_stab
F_init
F_Vdd
F_load
ΔF/ΔT
F_dynamic
F_24_Hold
F_1d
F_1y
F_20y
F_tot_20y
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
10 second averaging time
[3]
Referenced to (max frequency + min frequency)/2 over the
rated temperature range. Vc=Vdd/2 for VCTCXO
Initial frequency at 25°C at 48 hours after 2 reflows
Vdd ±5%
LVCMOS output, 15 pF ±10%. Clipped sinewave output,
10 kΩ || 10 pF ±10%
-40 to 105°C
0.5°C/min temperature ramp rate
Inclusive of frequency variation due to temperature,
±10%
supply variation,
±1.5
pF load variation and 24-hour aging
At 25°C, after 30-days of continued operation. Aging is
measured with respect to day 31
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
Complies with Stratum 3 per GR-1244-CORE. Actual
performance is better
Frequency Stability
–
Stratum 3 Grade
Rev 1.07
Page 4 of 41
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SiT5356
1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Table 1. Output Characteristics (continued)
Parameters
Duty Cycle
Rise/Fall Time
Output Voltage High
Output Voltage Low
Output Impedance
Symbol
DC
Tr, Tf
VOH
VOL
Z_out_c
Min.
45
0.8
90%
–
–
–
–
–
Output Voltage Swing
Rise/Fall Time
Start-up Time
V_out
Tr, Tf
T_start
0.8
–
–
Typ.
–
1.2
–
–
17
17
18
19
–
3.5
2.5
Max.
55
1.9
–
10%
–
–
–
–
1.2
4.6
3.5
Unit
%
ns
Vdd
Vdd
Ohms
Ohms
Ohms
Ohms
V
ns
ms
10% - 90% Vdd
IOH = +3 mA
IOL = -3 mA
Impedance looking into output buffer, Vdd = 3.3 V
Impedance looking into output buffer, Vdd = 3.0 V
Impedance looking into output buffer, Vdd = 2.8 V
Impedance looking into output buffer, Vdd = 2.5 V
Clipped sinewave output, 10 kΩ || 10 pF ±10%
20% - 80% Vdd, F_nom = 19.2 MHz
Time to first pulse, measured from the time Vdd reaches
90% of its final value. Vdd ramp time = 100 µs from 0 V to
Vdd
F_nom = 10 MHz. See
Timing Diagrams
section below
Time to first accurate pulse within rated stability, measured
from the time Vdd reaches 90% of its final value.
Vdd ramp time = 100 µs
Condition
LVCMOS Output Characteristics
Clipped Sinewave Output Characteristics
Start-up Characteristics
Output Enable Time
Time to Rated Frequency Stability
T_oe
T_stability
–
–
–
5
680
45
ns
ms
Note:
3. Measured 2 hours after startup in a temperature chamber with a constant temperature in still air.
Table 2. DC Characteristics
Parameters
Supply Voltage
Symbol
Vdd
Min.
2.25
2.52
2.7
2.97
Current Consumption
OE Disable Current
Idd
I_od
–
–
–
–
Typ.
2.5
2.8
3.0
3.3
44
48
43
47
Max.
2.75
3.08
3.3
3.63
53
57
51
55
Unit
V
V
V
V
mA
mA
mA
mA
F_nom = 19.2 MHz, No Load, TCXO and DCTCXO modes
F_nom = 19.2 MHz, No Load, VCTCXO mode
OE = GND, output weakly pulled down. TCXO, DCTCXO
OE = GND, output weakly pulled down. VCTCXO mode
Condition
Contact
SiTime
for 2.25 V to 3.63 V continuous supply
voltage support
Supply Voltage
Current Consumption
Rev 1.07
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