SiT2001B
Single-Chip, SOT23 Oscillator
Features
Applications
Any frequency between 1 MHz and 110 MHz accurate
to 6 decimal places
Operating temperature from -40°C to 85°C.
Refer to
SiT2018
for -40°C to 85°C option and
SiT2020
for -55°C to 125°C option
Excellent total frequency stability as low as ±20 ppm
Low power consumption of 3.5 mA typical
Fast start-up time of 5 ms
LVCMOS/HCMOS compatible output
5-pin SOT23-5: 2.9 mm x 2.8mm
Pb-free, RoHS and REACH compliant
For AEC-Q100 SOT23 Oscillators, refer to
SiT2024
and
SiT2025
Industrial, medical, automotive, avionics and other
high temperature applications
Industrial sensors, PLC, motor servo, outdoor
networking equipment, medical video cam, asset
tracking systems, etc.
Electrical Specifications
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and nominal supply voltage.
Table 1. Electrical Characteristics
Parameters
Output Frequency Range
Symbol
f
Min.
1
Typ.
–
–
–
–
–
–
Max.
110
Unit
MHz
Inclusive of Initial tolerance at 25°C, 1
st
year aging at 25°C,
and variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Condition
Frequency Range
Frequency Stability and Aging
Frequency Stability
F_stab
-20
-25
-50
+20
+25
+50
ppm
ppm
ppm
Operating Temperature Range
Operating Temperature
Range (ambient)
T_use
-20
-40
+70
+85
°C
°C
Extended Commercial
Industrial
Supply Voltage and Current Consumption
Supply Voltage
Vdd
1.62
2.25
2.52
2.7
2.97
2.25
Current Consumption
Idd
–
–
–
OE Disable Current
I_od
–
–
Standby Current
I_std
–
–
–
1.8
2.5
2.8
3.0
3.3
–
3.8
3.7
3.5
–
–
2.6
1.4
0.6
1.98
2.75
3.08
3.3
3.63
3.63
4.5
4.2
4.1
4.3
4.1
4.3
2.5
1.3
V
V
V
V
V
V
mA
mA
mA
mA
mA
A
A
A
No load condition, f = 20 MHz, Vdd = 2.8V, 3.0V or 3.3V
No load condition, f = 20 MHz, Vdd = 2.5V
No load condition, f = 20 MHz, Vdd = 1.8V
Vdd = 2.5V to 3.3V, OE = Low, Output in high Z state.
Vdd = 1.8V, OE = Low, Output in high Z state.
Vdd = 2.8V to 3.3V,
ST
= Low, Output is weakly pulled down
Vdd = 2.5V,
ST
= Low, Output is weakly pulled down
Vdd = 1.8V,
ST
= Low, Output is weakly pulled down
All Vdds
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
Vdd =1.8V, 20% - 80%
Vdd = 2.25V - 3.63V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V or 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V or 2.5V)
IOL = 2 mA (Vdd = 1.8V)
LVCMOS Output Characteristics
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
45
–
–
–
Output High Voltage
VOH
90%
–
–
1.0
1.3
–
–
–
55
2.0
2.5
2.0
–
%
ns
ns
ns
Vdd
Output Low Voltage
VOL
10%
Vdd
Rev. 1.02
April 19, 2018
www.sitime.com
SiT2001B
Single-Chip, SOT23 Oscillator
Table 1. Electrical Characteristics (continued)
Parameters
Input High Voltage
Input Low Voltage
Input Pull-up impedance
Symbol
VIH
VIL
Z_in
Min.
70%
–
50
2
Typ.
–
–
87
–
Max.
–
30%
150
–
Unit
Vdd
Vdd
k
M
Condition
Input Characteristics
Pin 3, OE or
ST
Pin 3, OE or
ST
Pin 3, OE logic high or logic low, or
ST
logic high
Pin 3,
ST
logic low
Measured from the time Vdd reaches its rated minimum value
f = 110 MHz.
For other frequencies, T_oe = 100 ns + 3 * clock periods
Measured from the time
ST
pin crosses 50% threshold
Startup and Resume Timing
Startup Time
Enable/Disable Time
Resume Time
T_start
T_oe
T_resume
–
–
–
–
–
Peak-to-peak Period Jitter
T_pk
–
–
RMS Phase Jitter (random)
T_phj
–
–
–
–
–
5
130
5
Jitter
RMS Period Jitter
T_jitt
1.8
1.8
12
14
0.5
1.3
3
3
20
25
0.9
2
ps
ps
ps
ps
ps
ps
f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 75 MHz, Vdd = 1.8V
f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 75 MHz, Vdd = 1.8V
f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz
ms
ns
ms
Table 2. Pin Description
Pin
1
2
Symbol
GND
NC
Power
No Connect
Output Enable
No connect
H : specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open : specified frequency output
3
OE/ ST /NC
̅ ̅̅
Standby
L: output is low (weak pull down). Device goes to sleep mode.
Supply current reduces to I_std.
Any voltage between 0 and Vdd or Open :
Specified frequency output. Pin 3 has no function.
Power supply voltage
Oscillator output
[2]
[1]
[1]
[1]
Top View
Functionality
Electrical ground
OE /
/ NC
NC
GND
No Connect
4
5
VDD
OUT
Power
Output
VDD
OUT
Figure 1. Pin Assignments
Notes:
1. In OE or
ST
mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If pin 3 needs to be left floating, use the NC option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Rev. 1.02
Page 2 of 16
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SiT2001B
Single-Chip, SOT23 Oscillator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specificat ions, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free
soldering guidelines)
Junction Temperature
[3]
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
Package
SOT23-5
[4]
JA, 4 Layer Board
(°C/W)
421
JC, Bottom
(°C/W)
175
Note:
4. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
Max Operating Temperature (ambient)
70°C
85°C
[5]
Maximum Operating Junction Temperature
80°C
95°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.02
Page 3 of 16
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SiT2001B
Single-Chip, SOT23 Oscillator
Test Circuit and Waveform
[6]
Test
Point
Vout
Vdd
tr
80% Vdd
Power
Supply
tf
5
15 pF
(including probe
and fixture
capacitance)
4
0.1µF
50%
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
1
2
3
Vdd
1k
Ω
OE/ST Function
Figure 2. Test Circuit
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Output Waveform
Timing Diagrams
90% Vdd
Vdd
50% Vdd
Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
[7]
ST Voltage
T_resume
CLK Output
HZ
CLK Output
HZ
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 4. Startup Timing (OE/
ST
Mode)
Figure 6. Standby Resume Timing (
ST
Mode Only)
Vdd
50% Vdd
T_oe
OE Voltage
OE Voltage
Vdd
50% Vdd
T_oe
CLK Output
HZ
CLK Output
HZ
T_oe: Time to re-enable the clock output
T_oe: Time to put the output in High Z mode
Figure 5. OE Enable Timing (OE Mode Only)
Note:
7. SiT2001 has “no runt” pulses and “no glitch” output during startup or resume.
Figure 7. OE Disable Timing (OE Mode Only)
Rev. 1.02
Page 4 of 16
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SiT2001B
Single-Chip, SOT23 Oscillator
Performance Plots
[8]
1.8
6.0
2.5
2.8
3.0
3.3
5.5
5.0
4.5
4.0
3.5
3.0
10
20
40
60
70
80
100
110
Frequency (MHz)
Frequency (ppm)
Idd (mA)
Temperature (°C)
Figure 8. Idd vs Frequency
Figure 9. Frequency vs Temperature
1.8
2.5
2.8
3.0
3.3
55
54
1.8
2.5
2.8
3.0
3.3
RMS period jitter (ps)
53
52
Duty cycle (%)
0
10
30
40
70
90
51
50
49
48
47
46
45
0
10
20
30
40
50
60
70
80
90
100
110
Frequency (MHz)
Frequency (MHz)
Figure 10. RMS Period Jitter vs Frequency
Figure 11. Duty Cycle vs Frequency
Rise time (ns)
Temperature (°C)
Fall time (ns)
Temperature (°C)
Figure 12. 20%-80% Rise Time vs Temperature
Figure 13. 20%-80% Fall Time vs Temperature
Rev. 1.02
Page 5 of 16
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