line losses (driven signal minus receiver threshold (340mV -
100mV = 240mV)). The signal is centered around +1.2V (Driver
Offset, V
OS
) with respect to ground as shown in Figure 4.
Note:
The steady-state voltage (V
SS
) peak-to-peak swing is twice the
differential voltage (V
OD
) and is typically 680mV.
2
3V
D
IN
D
OUT-
SINGLE-ENDED
D
OUT+
V
0D
0V
V
OH
V
OS
V
OL
+V
OD
0V (DIFF.)
0V
-V
OD
D
OUT+
- D
OUT-
DIFFERENTIAL OUTPUT
Note: The footprint of the UT54LVDSC031 is the same as the
industry standard Quad Differential (RS-422) Driver.
V
SS
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quiescent
current remains relatively flat versus switching frequency.
Whereas the RS-422 voltage mode driver increases
exponentially in most cases between 20 MHz - 50 MHz. This is
due to the overlap current that flows between the rails of the
device when the internal gates switch. Whereas the current mode
driver switches a fixed current between its output without any
substantial overlap current. This is similar to some ECL and
PECL devices, but without the heavy static I
CC
requirements of
the ECL/PECL design. LVDS requires 80% less current than
similar PECL devices. AC specifications for the driver are a
tenfold improvement over other existing RS-422 drivers.
The Three-State function allows the driver outputs to be
disabled, thus obtaining an even lower power state when the
transmission of data is not required.
Figure 4. Driver Output Levels
3
OPERATIONAL ENVIRONMENT
PARAMETER
Total Ionizing Dose (TID)
Single Event Latchup (SEL)
Neutron Fluence
1
Notes:
1. Guarnteed but not tested.
LIMIT
1.0E6
>100
1.0E13
UNITS
rad(Si)
MeV-cm
2
/mg
n/cm
2
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O4
PARAMETER
DC supply voltage
Voltage on any pin during operation
LIMITS
-0.3V to 6.0V
-0.3V to (V
DD
+ 0.3V)
Voltage on LVDS outputs during cold
spare
T
STG
P
D
T
J
Θ
JC
I
I
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
-0.3V to 6.0V
-65 to +150°C
1.25 W
+150°C
10°C/W
±
10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
4. During cold spare, all pins except LVDS outputs should not exceeed ±0.3V.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
4.5 to 5.5V
-55 to +125°C
0V to V
DD
4
DC ELECTRICAL CHARACTERISTICS*
1, 2
(V
DD
= 5.0V +10%; -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
V
IH
V
IL
V
OL
V
OH
I
IN4
I
CSOUT
V
OD1
ΔV
OD1
V
OS
ΔV
OS
V
CL3
I
OS3
I
OZ4
I
CCL4
I
CCZ4
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input leakage current
(TTL)
(TTL)
R
L
= 100Ω
R
L
= 100Ω
V
IN
= V
DD
-10
-10
250
CONDITION
MIN
2.0
V
SS
0.90
1.60
+10
+10
400
10
1.125
1.375
MAX
V
DD
0.8
UNIT
V
V
V
V
μA
μΑ
mV
mV
V
Cold Spare Leakage LVDS Outputs V
IN
=5.5V, V
DD
=V
SS
Differential Output Voltage
Change in Magnitude of V
OD
for
Complementary Output States
Offset Voltage
R
L
= 100Ω
(figure 5)
R
L
= 100Ω
(figure 5)
Voh + Vol
-
R
L
= 100Ω,
⎛
Vos = --------------------------
⎞
⎝
⎠
2
Change in Magnitude of V
OS
for
Complementary Output States
Input clamp voltage
Output Short Circuit Current
Output Three-State Current
R
L
= 100Ω
(figure 5)
I
CL
= -18mA
V
OUT
= 0V
2
EN = 0.8V and EN = 2.0 V,
V
OUT
= 0V or V
DD
R
L
= 100Ω all channels
V
IN
= V
DD
or V
SS
(all inputs)
D
IN
= V
DD
or V
SS
EN = V
SS
, EN = V
DD
-10
25
-1.5
5.0
+10
mV
V
mA
μΑ
Loaded supply current drivers
enabled
Loaded supply current drivers
disabled
mA
25.0
mA
10.0
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25
o
C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages.
2. Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
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FPGA/CPLD
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