700MHz, Crystal-to-LVDS
Frequency Synthesizer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
ICS8442I-90
DATA SHEET
General Description
The ICS8442I-90 is a general purpose, dual output
Crystal-to-Differential LVDS High Frequency Synthesizer. The
ICS8442I-90 has a selectable REF_CLK or crystal input. The
REF_CLK input accepts LVCMOS or LVTTL input levels and
translates them to LVDS levels. The VCO operates at a frequency
range of 250MHz to 700MHz. The VCO frequency is programmed in
steps equal to the value of the input reference or crystal frequency.
The VCO and output frequency can be programmed using the serial
or parallel interface to the configuration logic.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Dual differential LVDS outputs
FOUT1/nFOUT1 lags FOUT0/nFOUT0 by 90°
Selectable crystal oscillator interface or LVCMOS/LVTTL
REF_CLK
Output frequency range: 31.25MHz – 700MHz
Crystal input frequency range: 10MHz to 25MHz
VCO range: 250MHz – 700MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 7ps (maximum), (N= ÷1, ÷2, ÷4)
Cycle-to-cycle jitter: 34ps (maximum), (N= ÷1, ÷2)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For Replacement device use: 8442BYILF or 8T49N222
Block Diagram
VCO_SEL
XTAL_SEL
REF_CLK
Pullup
Pullup
Pin Assignment
VCO_SEL
nP_LOAD
M2
XTAL_IN
M4
M3
M0
M1
Pulldown
0
OSC
1
M5
M6
M7
M8
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9
TEST
XTAL_IN
XTAL_OUT
XTAL_OUT
REF_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
Pulldown
N0
÷
1
÷
2
N1
nc
FOUT0
nFOUT0
0
90˚Ø
1
TEST
FOUT1
nFOUT1
GND
VCO
÷
M
0
1
÷
4
÷
8
10 11 12 13 14 15 16
FOUT0
nFOUT0
nFOUT1
FOUT1
GND
V
DD
V
DD
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
Pulldown
Pulldown
Pulldown
Pulldown
CONFIGURATION
INTERFACE
LOGIC
9
ICS8442I-90
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
M[8:0]
N[1:0]
M5=Pullup; M[0:4], M[6:8]=Pulldown
Pulldown
2
ICS8442AKI-90 REVISION B JANUARY 31, 2014
1
©2014 Integrated Device Technology, Inc.
ICS8442I-90 Data Sheet
700MHZ, CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The ICS8442I-90 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
fundamental crystal is used as the input to the on-chip oscillator. The
output of the oscillator is fed into the phase detector. A 25MHz crystal
provides a 25MHz phase detector reference frequency. The VCO of
the PLL operates over a range of 250MHz to 700MHz. The output of
the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the
LVDS output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8442I-90 support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial.
Figure 1
shows the timing
diagram for each mode. In parallel mode, the nP_LOAD input is
initially LOW. The data on inputs M0 through M8 and N0 and N1 is
passed directly to the M divider and N output divider. On the
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_DATA, Shift Register Input
Output of M Divider
CMOS f
OUT
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and N bits
can be hardwired to set the M divider and N output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows: fVCO = fXTAL x M
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 25MHz reference are
defined as 10
M
28. The frequency out is defined as follows:
FOUT = fVCO = fXTAL x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T1
S
T0
H
NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M[0:8], N[0:1]
nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
NOTE: The NULL timing slot must be observed.
Figure 1. Parallel & Serial Load Operations
ICS8442AKI-90 REVISION B JANUARY 31, 2014
2
©2014 Integrated Device Technology, Inc.
ICS8442I-90 Data Sheet
700MHZ, CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1
2, 3, 4,
28, 29, 30,
31, 32
5, 6
7
8, 16
9
10, 13
11,
12
14,
15
Name
M5
M6, M7, M8,
M0, M1, M2,
M3, M4
N0, N1
nc
GND
TEST
V
DD
FOUT1,
nFOUT1
FOUT0,
nFOUT0
Input
Input
Type
Pullup
Pulldown
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Determines output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
No connect.
Power supply ground.
Test output which is ACTIVE in the serial mode of operation. Output driven LOW in
parallel mode. LVCMOS / LVTTL interface levels.
Core supply pins.
Differential clock outputs for the synthesizer. Lags FOUT0, nFOUT0 by 90°.
LVDS interface levels.
Differential clock outputs for the synthesizer. LVDS interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset causing
the true outputs FOUTx to go low and the inverted outputs nFOUTx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Assertion of MR
does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on the rising
edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Pullup
Pulldown
Selects between crystal oscillator or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects REF_CLK when LOW.
LVCMOS / LVTTL interface levels.
Single-ended reference clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into
M divider, and when data present at N1:N0 sets the N output divider value.
LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode. In bypass mode,
VCO_SEL = 0, the differential outputs are phase aligned. NOTE 1.
LVCMOS / LVTTL interface levels.
Description
Input
Unused
Power
Output
Power
Output
Output
Pulldown
17
MR
Input
Pulldown
18
19
20
21
22
23
24,
25
26
S_CLOCK
S_DATA
S_LOAD
V
DDA
XTAL_SEL
REF_CLK
XTAL_OUT,
XTAL_IN
nP_LOAD
Input
Input
Input
Power
Input
Input
Input
Pulldown
Pulldown
Pulldown
Input
Pulldown
27
VCO_SEL
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
NOTE 1: In bypass mode, VCO_SEL = 0, the differential outputs are phase aligned.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
3
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2014 Integrated Device Technology, Inc.
ICS8442AKI-90 REVISION B JANUARY 31, 2014
ICS8442I-90 Data Sheet
700MHZ, CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
L
H
S_CLOCK
X
X
X
L
L
X
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. When HIGH, forces the outputs to a differential
LOW state (FOUTx = LOW and nFOUTx = HIGH), but does
not effect loaded M, N, and T values.
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
= Rising edge transition
= Falling edge transition
Table 3B. Programmable VCO Frequency Function Table (NOTE 1)
VCO Frequency
(MHz)
250
275
•
•
650
675
700
256
M Divide
10
11
•
•
26
27
28
M8
0
0
•
•
0
0
0
128
M7
0
0
•
•
0
0
0
64
M6
0
0
•
•
0
0
0
32
M5
0
0
•
•
0
0
0
16
M4
0
0
•
•
1
1
1
8
M3
1
1
•
•
1
1
1
4
M2
0
0
•
•
0
0
1
2
M1
1
1
•
•
1
1
0
1
M0
0
1
•
•
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or REF_CLK input frequency of 25MHz.
Table 3C. Programmable Output Divider Function Table
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
1 (default)
2
4
8
Output Frequency (MHz)
Minimum
250
125
62.5
31.25
Maximum
700
350
175
87.5
ICS8442AKI-90 REVISION B JANUARY 31, 2014
4
©2014 Integrated Device Technology, Inc.
ICS8442I-90 Data Sheet
700MHZ, CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
37C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.16
Typical
3.3
3.3
Maximum
3.465
V
DD
210
16
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
S_LOAD, REF_CLK,
M[0:4], M[6:8], N0, N1, MR,
S_CLOCK, S_DATA, nP_LOAD
M5, XTAL_SEL, VCO_SEL
Input
Low Current
Output
High Voltage
Output
Low Voltage
S_LOAD, REF_CLK,
M[0:4], M[6:8], N0, N1, MR,
S_CLOCK, S_DATA, nP_LOAD
M5, XTAL_SEL, VCO_SEL
V
OH
V
OL
TEST; NOTE 1
TEST; NOTE 1
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
V
V
I
IL
NOTE 1: Outputs terminated with 50
to V
DD
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
ICS8442AKI-90 REVISION B JANUARY 31, 2014
5
©2014 Integrated Device Technology, Inc.
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