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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTP4N40E/D
Designer’s™ Data Sheet
TMOS E−FET.™
Power Field Effect Transistor
N−Channel Enhancement−Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage−blocking capability without
degrading performance over time. In addition, this advanced TMOS
E−FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain−to−source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
•
Robust High Voltage Termination
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
MTP4N40E
Motorola Preferred Device
TMOS POWER FET
4.0 AMPERES
400 VOLTS
R
DS(on)
= 1.8 OHM
®
D
G
S
CASE 221A−06, Style 5
TO−220AB
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage — Continuous
— Non−Repetitive (t
p
≤
10 ms)
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (t
p
≤
10
µs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 10 Vdc, Peak I
L
= 4.0 Apk, L = 25 mH, R
G
= 25
Ω)
Thermal Resistance — Junction to Case
— Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
T
J
, T
stg
E
AS
200
R
θJC
R
θJA
T
L
1.7
62.5
260
°C/W
°C
Value
400
400
±
20
±
40
4.0
3.0
14
74
0.59
−55 to 150
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C
mJ
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola TMOS
©
Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
MTP4N40E
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 400 Vdc, V
GS
= 0 Vdc)
(V
DS
= 400 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(1)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
µAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 2.0 Adc)
Drain−to−Source On−Voltage
(V
GS
= 10 Vdc, I
D
= 4.0 Adc)
(V
GS
= 10 Vdc, I
D
= 2.0 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 2.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 320 Vdc, I
D
= 4.0 Adc,
V
GS
= 10 Vdc)
(V
DD
= 200 Vdc, I
D
= 4.0 Adc,
V
GS
= 10 Vdc,
Vdc
R
G
= 9.1
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 4.0 Adc, V
GS
= 0 Vdc)
(I
S
= 4.0 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
—
—
t
rr
(I
S
= 4.0 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
L
D
—
—
L
S
—
7.5
—
3.5
4.5
—
—
nH
nH
t
a
t
b
Q
RR
—
—
—
—
0.9
0.78
200
99
101
1.03
1.6
—
—
—
—
—
µC
ns
Vdc
—
—
—
—
—
—
—
—
9.0
11
18
14
13
2.5
6.0
7.0
20
30
30
30
21
—
—
—
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
Vd
Vd
f = 1.0 MHz)
C
iss
C
oss
C
rss
—
—
—
440
72
14
616
100
19.6
pF
V
GS(th)
2.0
—
R
DS(on)
V
DS(on)
—
—
g
FS
1.8
—
—
2.5
8.6
4.3
—
mhos
—
3.0
6.0
1.3
4.0
—
1.8
Vdc
mV/°C
Ohms
Vdc
V
(BR)DSS
400
—
I
DSS
—
—
I
GSS
—
—
—
—
10
100
100
nAdc
—
420
—
—
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP4N40E
TYPICAL ELECTRICAL CHARACTERISTICS
8
I D , DRAIN CURRENT (AMPS)
7
6
5
4
3
2
1
0
0
2
6
10
14
8
12
16
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
4
18
20
5V
6V
T
J
= 25°C
V
GS
= 10 V
7V
I D , DRAIN CURRENT (AMPS)
8
7
6
5
4
3
2
1
0
2
25°C
2.5 3
100°C
T
J
= −55°C
8.5
9
V
DS
≥
10 V
9V
8V
3.5 4 4.5 5 5.5 6 6.5 7 7.5 8
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
4
3.5
3
2.5
2
1.5
1
0.5
0
0
1
2
3
5
6
4
I
D
, DRAIN CURRENT (AMPS)
7
8
− 55°C
25°C
V
GS
= 10 V
T
J
= 100°C
2.25
T
J
= 25°C
2
1.75
1.5
1.25
1
0.75
0.5
0
0.5 1
1.5 2
2.5 3 3.5 4 4.5 5 5.5 6
I
D
, DRAIN CURRENT (AMPS)
6.5 7
7.5
15 V
V
GS
= 10 V
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.5
2.0
V
GS
= 10 V
I
D
= 2 A
I DSS , LEAKAGE (nA)
1000
V
GS
= 0 V
T
J
= 125°C
100
2.25
1.75
1.5
1.0
100°C
1.25
0.75
0.5
0
−50
10
0.25
−25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
1
0
50
100
200
300
150
250
350
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
400
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTP4N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain−gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
G(AV)
) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V
GS
remains virtually constant at a level known as
the plateau voltage, V
SGP
. Therefore, rise and fall times may
be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when cal-
culating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
800
700
C, CAPACITANCE (pF)
600
500
400
300
200
100
0
10
C
rss
C
iss
V
DS
= 0 V
V
GS
= 0 V
T
J
= 25°C
C
iss
C
oss
C
rss
5
V
GS
0
V
DS
5
10
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
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