AS8S128K32
128K x 32 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY SPECIFICATIONS
• SMD 5962-95595 (-Q); SMD 5962-93187 (-P or -PN);
MIL-STD-883
SRAM
GENERAL DESCRIPTION
8, 21, 28, 39 are no connects (PN
66 Lead PGA- Pins
The AS8S128K32 is a 4 Megabit CMOS SRAM Module or-
ganized as 128Kx32-bits and user configurable to 256Kx16 or
512Kx8. The AS8S128K32 achieves high speed access, low
power consumption and high reliability by employing advanced
CMOS memory technology.
The military temperature grade product is suited for military
applications.
The AS8S128K32 is offered in a ceramic quad flatpack module
per SMD-5962-95595 with a maximum height of 0.140 inches.
FEATURES
• Operation with single 5V supply • Built in decoupling caps for
• 2V Data Retention, Low power
low noise operation
standby
• Organized as 128K x32; User
• Vastly improved Icc Specs
configured as 256Kx16 or
• Access times of 12, 15, 17, 20,
512K x8
25, 35, and 45 ns
• TTL Compatible Inputs and
• Low power CMOS
Outputs
AS8S128K32
CE4
WE4
SRAM
OPTIONS
Timing
12ns
15ns
17ns
20ns
Markings
-12
-15
-17
-20
Timing
25ns
35ns
45ns
Markings
-25
-35
-45
128K x 8
128K x 8
128K x 8
PIN ASSIGNMENT
(Top View)
(Top View)
PIN ASSIGNMENT
(Top View)
Package
Ceramic Quad Flatpack
Pin Grid Array -8 Series
on pins 8, 21,
Markings
28, 39
Q (No. 702); Q1
P
ASSIGNMENT
PIN
(No. 802); PN* (No. 802)
AS8S128K32
*No connect
SRAM
AS8S128K32
SRAM
68 Lead CQFP
(Q & Q1)
66 Lead PGA- Pins 8, 21, 28, 39 are grounds (P)
66 Lead
PGA- Pins 8,
21, 28, 39 are
grounds (P)
66 Lead PGA- Pins 8, 21, 28, 39 are grounds (P)
66 Lead PGA- Pins 8, 21, 28, 39 are no connects (PN)
Vcc
A11
A12
A13
A14
A15
A16
CS2\
OE\
CS4\
NC
NC
NC
NC
NC
NC
NC
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O
5
I/O
6
I/O
7
GND
I/O 8
I/O
9
I/O
10
I/O 11
I/O 12
I/O 13
I/O 14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
NC
A0
A1
A2
A3
A4
A5
CS1\
GND
CS3\
WE\
A6
A7
A8
A9
A10
Vcc
68
Lead CQFP (Q & Q1)
68
Lead CQFP (Q & Q1)
This device is also offered
in a 1.075 inch square
ceramic pin grid array per
SMD 5692-93187, which
has a maximum height of
0.195 inches. This pack-
age is also a low profile,
multi-chip module design
reducing height require-
ments to a minimum.
CE3
WE3
M2
M1
M0
128K x 8
I/O 24 - I/O 31
I/O 16 - I/O 23
I/O 8 - I/O 23
PIN
makes use of
This module
ASSIGNMENT
(Top View)
a low profile, mutlichip
module design.
CQFP (Q & Q1)
68 Lead
M3
CE2
WE2
CE1
WE1
OE
A0 - 16
I/O 0 - I/O 7
66 Lead PGA- Pins 8, 21, 28, 39 are grounds (P)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
68 Lead
CQFP
(BQFP)
Military SMD
Pinout Option
66 Lead
PGA- Pins 8,
21, 28, 39 are
no connects
(PN)
x8
66 Lead PGA- Pins 8, 21, 28, 39 are no connects (PN)
CE3
WE3
M2
128K x 8
AS8S128K32
Rev. 4.5 08/13
66 Lead PGA- Pins 8, 21, 28, 39 are no connects (PN)
1
CE4
Micross
WE4
Components reserves the right to change products or specifications without notice.
M3
I/O 24 - I/O 31
AS8S128K32
ABSOLUTE MAXIMUM RATINGS*
Voltage of Vcc Supply Relative to Vss................-1V to +7V
Storage Temperature...................................-65°C to +150°C
Short Circuit Output Current(per I/O).........................20mA
Voltage on Any Pin Relative to Vss..............-.5V to Vcc+1V
Maximum Junction Temperature**...........................+175°C
SRAM
*Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device.
This is a stress rating only and functional operation on the device
at these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may
affect reliability.
**Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow. See the Application Infor-
mation section at the end of this datasheet for more information.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C<TA<125°C; Vcc = 5v ±10%)
µΑ
µΑ
µΑ
PARAMETER
Power Supply Current:
Operating
CONDITIONS
CE\<V
IL
; V
CC
=MAX
f = MAX = 1/t
RC
(MIN)
Outputs Open
CE\>V
IH
; V
CC
=MAX
f = MAX = 1/t
RC
(MIN)
Outputs Open
SYM
I
cc
-12
250
-15
200
-17
175
MAX
-20
150
-25
140
-35
130
-45
120
UNITS NOTES
mA
3, 13
(1)
I
SBT1
40
40
40
35
35
30
30
mA
(1)
Power Supply Current:
Standby
CE\ > V
cc
-0.2V; Vcc = MAX
V
IL
< V
ss
+0.2V;
V
IH
> V
CC
-0.2V; f = 0 Hz
CE\ > Vcc -0.2V; Vcc = MAX
V
IL
< Vss +0.2V;
V
IH
> Vcc -0.2V; f = 0 Hz
"L" Version Only
I
SBC1
30
30
30
30
30
30
30
mA
(2)
I
SBC2
20
20
20
20
20
20
20
mA
(2)
NOTE:
1) Address switching sequence A, A+1, A+2, etc.
2) 1/2 input at HIGH, 1/2 input at LOW.
AS8S128K32
Rev. 4.5 08/13
Micross Components reserves the right to change products or specifications without notice.
2
Austin Semiconductor, Inc.
Austin Semiconductor, Inc.
AS8S128K32
AS8S128K32
AS8S128K32
NOTES
NOTES
NOTES
4
4
4
4
4
4
4
4
4
4
44
SRAM
SRAM
SRAM
CAPACITANCE TABLE
(V = 0V, f f 1 MHz, T T= 25
o
C)
CAPACITANCE TABLE
(V
IN IN
= 0V, = = 1 MHz,
A A
= 25
o
C)
CAPACITANCE TABLE
PARAMETER
f = 1 MHz, T
A
= 25
o
C)
UNITS
(V
IN
= 0V,
SYMBOL
MAX
SYMBOL
PARAMETER
MAX
UNITS
C
ADD
C
ADD
C
ADD
C
OE
C
OEOE
C
SYMBOL
C
C
C
C
WE,CE
CE
C
WE,
WE,
C
CE
C
C
IO
C
IO IO
A0A0A18 Capacitance
- - A18 Capacitance
A0 - A18 Capacitance
OE\ Capacitance
OE\ Capacitance
OE\ Capacitance
PARAMETER
4040
40
4040
40
MAX
UNITS
pFpF
pF
WE\ and CE\
WE\ and CE\
Capacitance
WE\ and CE\ Capacitance
I/O
I/O
0- I/O 31 Capacitance
I/O 0- 0- I/O 31 Capacitance
I/O 31 Capacitance
20
2020
20
2020
pFpF
pF
pF
pFpF
pF
pFpF
TRUTH TABLE
TRUTH TABLE
MODE
MODE
Read
Read
Write
Write
Standby
Standby
Not Selected
Not Selected
OE\
OE\
L L
XX
XX
HH
CE\
CE\
L L
L L
HH
L L
WE\
WE\
HH
L L
XX
HH
I/O
I/O
QQ
DD
HIGH
HIGH Z Z
HIGH
HIGH Z Z
POWER
POWER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
STANDBY
STANDBY
ACTIVE
ACTIVE
AC TEST CONDITIONS
AC TEST CONDITIONS
AC TEST CONDITIONS
TEST SPECIFICATIONS
TEST SPECIFICATIONS
Input
SPECIFICATIONS
TEST
pulse levels........................................VSS 3V
Input pulse levels........................................VSS to to 3V
I
I
OLOL
Current Source
Current Source
Device
Device
Under
Under
Test
Test
-
+
+
-
+
Input rise and fall times..........................................5ns
Input pulse levels........................................VSS to 3V
Input rise and fall times..........................................5ns
Input timing reference levels.................................1.5V
Input rise and fall times..........................................5ns
Input timing reference levels.................................1.5V
Output reference levels........................................1.5V
Input
reference levels........................................1.5V
Output
timing reference levels.................................1.5V
Output load.............................................See Figures
Output reference levels........................................1.5V
Output load.............................................See Figures 1 1
Output load.............................................See Figures 1
VzVz = 1.5V
= 1.5V
(Bipolar
(Bipolar
Supply)
Supply)
+
Ceff 50pf
Ceff = = 50pf
Current Source
Current Source
I
I
OHOH
NOTES:
NOTES:
NOTES:
VzVzprogramable from -2V to + 7V.
is is programable from -2V to + 7V.
Figure
Figure 1 1
Figure 1
and
programmable
-2V
0 0 to
Vz is
I
OH
I
OH
programmable from
+ 7V.
mA.
I
OL
Iand
programable from
from
to
to 1616 mA.
OL
I
OL
and
typically the midpoint of Vand V
mA.
VzVz typically the midpoint
from
OH OH
and
OL
.
OL
.
is is
I
OH
programmable
of V
0 to 16
V
Vz
and I
OH
are adjusted to
of V
OH
typical
.
resistive load
I
OL
I
OL
is typically the midpoint
simulate
and V
OL
resistive load
and I
OH
are adjusted to simulate a a typical
circuit.
I
OL
and
circuit.
I
OH
are adjusted to simulate a typical resistive load
circuit.
AS8S128K32
AS8S128K32
Rev. 06/05
Rev. 4.1 4.1 06/05
AS8S128K32
Rev. 4.5 08/13
33
3
Austin Semiconductor, reserves the the to change products or specifications without notice.
Austin Semiconductor, Inc. Inc. reserves rightright to change products or specifications without notice.
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
°C≤TA≤125°C; Vcc = 5v ±10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in Low-Z
Chip disable to output in High-Z
Chip enable to power-up time
Chip disable to power-down time
Output enable access time
Output enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-z
Write enable to output in High-Z
-12
-15
-17
-20
-25
-35
-45
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
RC
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
t
t
t
t
12
12
12
2
2
6.5
0
12
5.5
0
6
12
10
10
0
1
10
10
7
0
2
1
1
15
15
15
2
2
7
0
15
6
0
6
15
12
12
0
1
12
12
8
0
2
6.5
1
1
17
17
17
2
2
8
0
17
7
0
7
17
12
12
0
1
12
12
9
0
2
7
1
1
20
20
20
2
2
9
0
20
7
0
7
20
15
15
0
1
15
15
10
0
2
9
10
25
25
25
2
2
10
0
25
8
0
9
25
17
17
0
1
17
17
12
0
2
11
35
35
35
2
2
14
0
35
12
0
12
35
20
20
0
1
20
20
15
0
2
14
45
45
45
2
2
15
0
45
12
0
12
45
22
22
0
1
20
20
15
0
2
15
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
4
4
4, 6
4, 6, 7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
t
AW
t
AS
t
AH
t
t
WP1
WP2
t
DS
t
DH
t
LZWE
t
HZWE
4, 6, 7
4, 6, 7
NOTES:
1) Spec listed is for OE\ = HIGH condition. For OE\ = LOW condition
t
WP1 =
t
WP2 = 15 ns MIN.
AS8S128K32
Rev. 4.5 08/13
Micross Components reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
NOTES
1. All voltages referenced to V
SS
(GND).
NOTES
2. -3v for pulse width <20ns.
1. All voltages referenced to V
SS
(GND).
3. I
CC
is
pulse width
output
2. -3v for
dependent on
<20ns.
loading and cycle rates.
The specified value applies with the outputs
3. I
CC
is dependent on output loading and cycle rates.
1
The
and f=
open,
specified value
t
applies with the outputs
H
Z.
RC(MIN)
1
open, and f=
H
Z.
t
RC(MIN)
4. This parameter is sampled.
5. Test conditions as specified
4. This parameter is sampled.
with output loading as
shown
conditions as specified with output
5. Test
in Fig. 1 unless otherwise noted.
loading as
6. t
HZCE
,
Fig. 1 unless
are specified with
shown in
t
HZOE
and t
HZWE
otherwise noted.
C
L
= 5pF
as
t
6.
in Fig.
t
2. Transition is measured +/- 200
C
L
= 5pF
,
and t
HZWE
are specified with
mV
HZCE HZOE
typical from steady state
measured +/- 200 mV
as in Fig. 2. Transition is
coltage, allowing for actual
tester RC time constant.
typical from steady state coltage, allowing for actual
tester RC time constant.
AS8S128K32
SRAM
SRAM
AS8S128K32
7. At any given temperature and voltage condition,
t
HZCE
,
any given temperature and
is less
condition,
7. At
is less than t
LZCE
, and t
HZWE
voltage
than t
LZWE
.
t
8.
?W/E
is HIGH
LZCE
READ
HZWE
is less than t
LZWE
.
, is less than t
for
, and t
cycle.
HZCE
9. Device
HIGH for READ cycle.
8.
?W/E
is
is continuously selected. Chip enables and output
enable are held in their active state.
9. Device is continuously selected. Chip enables and output
10. Address valid prior to or
state.
enable are held in their active
coincident with latest occurring
chip enable.
10. Address valid prior to or coincident with latest occurring
11.
enable.
chip
t
RC
= READ cycle time.
12.
t =
enable
cycle time.
11.
Chip
READ
(?C/E) and write enable (?W/E) can initiate and
RC
terminate a WRITE cycle.
12. Chip enable (?C/E) and write enable (?W/E) can initiate
13. 32 bit operation
and terminate a WRITE cycle.
13. 32 bit operation
V
CC
for
DESCRIPTION
Retention Data
V
CC
for Retention Data
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
SYMBOL
MIN
MAX
CONDITIONS
CONDITIONS
Data Retention Current
Data Retention Current
Chip Deselect to Data
Chip Deselect
Retention Time
to Data
Retention Time
Operation Recovery Time
Operation Recovery Time
CE\ > V
CC
- 0.2V
CE\ > V
CC
- 0.2V
V
IN
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V
SYMBOL
V
DR
V
DR
V
CC
= 2.0V
I
CCDR
V
CC
= 2.0V
I
CCDR
V
CC
= 3V
I
CCDR
V
CC
= 3V
I
CCDR
t
CDR
t
CDR
t
R
t
R
MIN
2
2
--
--
--
--
0
0
t
RC
t
RC
UNITS
NOTES
MAX
--
UNITS
V
NOTES
--
V
10
mA
6
mA
12
mA
11.6
mA
--
ns
4
--
ns
4
ns
4, 11
ns
4, 11
LOW V
CC
DATA RETENTION WAVEFORM
LOW V
CC
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vcc
V
IH
4.5V
VDR
>2V
4.5V
tCDR
VDR
tR
CE\
V
IL
AS8S128K32
Rev. 4.1 06/05
AS8S128K32
Rev. 4.5 08/13
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5
Micross Components reserves the right to change products or specifications without notice.
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
