Low Power Audio Codec
SSM2602
FEATURES
Stereo, 24-bit analog-to-digital and digital-to-analog converters
DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
Highly efficient headphone amplifier
Stereo line input and monaural microphone input
Low power
7 mW stereo playback (1.8 V/1.5 V supplies)
14 mW record and playback (1.8 V/1.5 V supplies)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital core: 1.5 V to 3.6 V
Digital I/O: 1.8 V to 3.6 V
256/384 oversampling rate in normal mode; 250/272 over-
sampling rate in USB mode
Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,
and 96 kHz
28-lead, 5 mm × 5 mm LFCSP (QFN) package
GENERAL DESCRIPTION
The SSM2602 is a low power, high quality stereo audio codec
for portable digital audio applications with one set of stereo
programmable gain amplifier (PGA) line inputs and one
monaural microphone input. It features two 24-bit analog-to-
digital converter (ADC) channels and two 24-bit digital-to-
analog (DAC) converter channels.
The SSM2602 can operate as a master or a slave. It supports
various master clock frequencies, including 12 MHz or 24 MHz
for USB devices; standard 256 f
S
or 384 f
S
based rates, such as
12.288 MHz and 24.576 MHz; and many common audio sampling
rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 24 kHz,
22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.
The SSM2602 can operate at power supplies as low as 1.8 V for
the analog circuitry and as low as 1.5 V for the digital circuitry.
The maximum voltage supply is 3.6 V for all supplies.
The SSM2602 software-programmable stereo output options
provide the user with many application possibilities because the
device can be used as a headphone driver or as a speaker driver.
Its volume control functions provide a large range of gain
control of the audio signal.
The SSM2602 is specified over the industrial temperature range
of −40°C to +85°C. It is available in a 28-lead, 5 mm × 5 mm
lead frame chip scale package (LFCSP).
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
AVDD
MICBIAS
–34.5dB TO +33dB,
1.5dB STEP
FUNCTIONAL BLOCK DIAGRAM
VMID AGND
DBVDD DGND DCVDD
HPVDD PGND
SSM2602
BYPASS
SIDETONE
6dB TO 15dB/MUTE 3dB STEP
–73dB TO +6dB,
1dB STEP
RHPOUT
RLINEIN
MUX
ADC
DAC
ROUT
MICIN
0dB/20dB/
40dB BOOST
DIGITAL
PROCESSOR
LOUT
MUX
ADC
DAC
LHPOUT
–34.5dB TO +33dB,
1.5dB STEP
LLINEIN
6dB TO 15dB/MUTE 3dB STEP
–73dB TO +6dB,
1dB STEP
SIDETONE
BYPASS
CLK
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/ XTO CLKOUT
XTI
PBDAT RECDAT BCLK PBLRC RECLRC MODE CSB
SDIN SCLK
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
06858-001
SSM2602
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Filter Characteristics ....................................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Converter Filter Response......................................................... 10
Digital De-Emphasis .................................................................. 11
Theory of Operation ...................................................................... 12
Digital Core ................................................................................. 12
ADC and DAC............................................................................ 12
ADC High Pass and DAC De-Emphasis Filters ..................... 12
Automatic Level Control (ALC)............................................... 13
Analog Interface ......................................................................... 14
Digital Audio Interface .............................................................. 16
Software Control Interface........................................................ 18
Typical Application Circuits ......................................................... 19
Register Map ................................................................................... 20
Register Map Details ...................................................................... 21
Left-Channel ADC Input Volume, Address 0x00.................. 21
Right-Channel ADC Input Volume, Address 0x01 ............... 22
Left-Channel DAC Volume, Address 0x02............................. 23
Right-Channel DAC Volume, Address 0x03 .......................... 23
Analog Audio Path, Address 0x04 ........................................... 24
Digital Audio Path Control, Address 0x05 ............................. 24
Power Management, Address 0x06.......................................... 25
Digital Audio I/F, Address 0x07 ............................................... 26
Sampling Rate, Address 0x08.................................................... 26
Active, Address 0x09.................................................................. 29
Reset, Address 0x0F ................................................................... 29
ALC Control 1, Address 0x10................................................... 30
ALC Control 2, Address 0x11................................................... 30
Noise Gate, Address 0x12.......................................................... 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
2/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
SSM2602
SPECIFICATIONS
T
A
= 25°C, AVDD = DVDD = 3.3 V, PVDD = 3.3 V, 1 kHz signal, f
S
= 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted.
Table 1.
Parameter
RECOMMENDED OPERATING CONDITIONS
Analog Voltage Supply (AVDD)
Digital Power Supply
Ground (AGND, PGND, DGND)
POWER CONSUMPTION
Power-Up
Stereo Record (1.5 V and 1.8 V)
Stereo Record (3.3 V)
Stereo Playback (1.5 V and 1.8 V)
Stereo Playback (3.3 V)
Power-Down
LINE INPUT
Input Signal Level (0 dB)
Input Impedance
Min
1.8
1.5
Typ
3.3
3.3
0
Max
3.6
3.6
Unit
V
V
V
Conditions
7
22
7
22
40
1 × AVDD/3.3
200
10
480
10
90
84
−80
−75
80
0
1.5
−80
1
85
−70
50
80
10
10
0.75 × AVDD
3
40
mW
mW
mW
mW
μW
V rms
kΩ
kΩ
kΩ
pF
dB
dB
dB
dB
dB
dB
dB
dB
V rms
dB
dB
dB
dB
kΩ
pF
V
mA
nV/√Hz
PGA gain = 0 dB
PGA gain = +33 dB
PGA gain = −34.5 dB
PGA gain = 0 dB, AVDD = 3.3 V
PGA gain = 0 dB, AVDD = 1.8 V
−1 dBFS input, AVDD = 3.3 V
−1 dBFS input, AVDD = 1.8 V
Input Capacitance
Signal-to-Noise Ratio (A-Weighted)
Total Harmonic Distortion (THD)
Channel Separation
Programmable Gain
Gain Step
Mute Attenuation
MICROPHONE INPUT
Input Signal Level
Signal-to-Noise Ratio (A-Weighted)
Total Harmonic Distortion
Power Supply Rejection Ratio
Mute Attenuation
Input Resistance
Input Capacitance
MICROPHONE BIAS
Bias Voltage
Bias Current Source
Noise in the Signal Bandwidth
LINE OUTPUT
DAC
Full-Scale Output
Signal-to-Noise Ratio (A-Weighted)
THD + N
Power Supply Rejection Ratio
Channel Separation
70
−34.5
+33.5
Microphone gain = 0 dB
(R
SOURCE
= 40 kΩ)
0 dBFS input, 0 dB gain
20 Hz to 20 kHz
−1 dBFS input DAC + line output
85
1 × AVDD/3.3
100
94
−80
−75
50
80
V rms
dB
−70
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
Rev. 0 | Page 3 of 32
SSM2602
Parameter
HEADPHONE OUTPUT
Full-Scale Output Voltage
Maximum Output Power
Signal-to-Noise Ratio (A-Weighted)
THD + N
Power Supply Rejection Ratio
Mute Attenuation
LINE INPUT TO LINE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
Total Harmonic Distortion
Power Supply Rejection
MICROPHONE INPUT TO
HEADPHONE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
Power Supply Rejection Ratio
Programmable Attenuation
Gain Step
Mute Attenuation
Min
Typ
1 × AVDD/3.3
30
60
96
90
−65
−60
50
80
1 × AVDD/3.3
92
86
−80
−80
50
Max
Unit
V rms
mW
mW
dB
dB
dB
dB
dB
V rms
dB
dB
dB
Conditions
85
R
L
= 32 Ω
R
L
= 16 Ω
AVDD = 3.3 V
AVDD = 1.8 V
P
OUT
= 10 mW
P
OUT
= 20 mW
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
1 × AVDD/3.3
94
88
50
6
3
80
15
V rms
dB
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
DIGITAL FILTER CHARACTERISTICS
Table 2.
Parameter
ADC FILTER
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
High-Pass Filter Corner Frequency
Min
0
0.5 f
S
±0.04
0.555 f
S
−61
3.7
10.4
21.6
0
0.5 f
S
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Core Clock Tolerance
Frequency Range
Jitter Tolerance
±0.04
0.555 f
S
−61
8.0
50
13.8
0.445 f
S
Typ
Max
0.445 f
S
Unit
Hz
Hz
dB
Hz
dB
Hz
Hz
Hz
Hz
Hz
dB
Hz
dB
MHz
ps
Conditions
±0.04 dB
−6 dB
f > 0.567 f
S
−3 dB
−0.5 dB
−0.1 dB
±0.04 dB
−6 dB
DAC FILTER
Pass Band
f > 0.565 f
S
Rev. 0 | Page 4 of 32
SSM2602
TIMING CHARACTERISTICS
Table 3. I
2
C® Timing
Parameter
t
SCS
t
SCH
t
PH
t
PL
f
SCLK
t
DS
t
DH
t
RT
t
FT
t
HCS
t
MIN
600
600
600
1.3
0
100
Limit
t
MAX
Unit
ns
ns
ns
μs
kHz
ns
ns
ns
ns
ns
t
SCH
t
PL
SCLK
526
900
300
300
600
Description
Start condition setup time
Start condition hold time
SCLK pulse width high
SCLK pulse width low
SCLK frequency
Data setup time
Data hold time
SDIN and SCLK rise time
SDIN and SCLK fall time
Stop condition setup time
t
HCS
t
DS
t
PH
t
DH
t
FT
t
SCS
06858-036
SDIN
t
RT
Figure 2. I
2
C Timing
Table 4. SPI Timing
Parameter
t
DSU
t
DHO
t
SCH
t
SCL
t
SCS
t
CSS
t
CSH
t
CSL
t
PS
t
MIN
20
20
20
20
60
20
20
20
0
Limit
t
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CSL
t
SCH
t
SCL
SCLK
5
Description
SDIN to SCLK setup time
SCLK to SDIN hold time
SCLK pulse width high
SCLK pulse width low
SCLK rising edge to CSB rising edge
CSB rising to SCLK rising
CSB pulse width high
CSB pulse width low
Pulse width of spikes to be suppressed
t
CSH
CSB
t
SCS
t
CSS
t
DSU
SDIN
t
DHO
Figure 3. SPI Timing
Rev. 0 | Page 5 of 32
06858-024
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
