A5833
BiMOS II 32-Bit Serial Input Latched Driver
Last Time Buy
These parts are in production but have been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: May 2, 2005
Deadline for receipt of LAST TIME BUY orders: October 28, 2005
Recommended Substitutions:
For new customers or new applications, refer to the
A6833.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.
5833
UCN5833EP
SERIAL DATA OUT
POWER GROUND
OUTPUT ENABLE
SERIAL DATA IN
BiMOS II 32-BIT SERIAL-INPUT,
LATCHED DRIVER
Designed to reduce logic supply current, chip size, and system
cost, the UCN5833A/EP integrated circuits offer high-speed operation
for thermal printers. These devices can also be used to drive multi-
plexed LED displays or incandescent lamps within their 125 mA peak
output current rating. The combination of bipolar and MOS technolo-
gies gives BiMOS II smart power ICs an interface flexibility beyond the
reach of standard buffers and power driver circuits.
39
38
37
36
Data Sheet
26185.16A*
STROBE
LOGIC
SUPPLY
CLOCK
OUT
32
41
OUT
1
NC
CLK
44
43
OE
42
V
DD
1
ST
4
40
5
6
3
2
NC
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
OUT
9
OUT
10
OUT
11
OUT
12
7
8
9
10
OUT
31
OUT
30
OUT
29
OUT
28
OUT
27
OUT
26
OUT
25
OUT
24
OUT
23
OUT
22
OUT
21
11
12
13
14
15
16
17
35
34
33
32
31
30
29
These 32-bit drivers have bipolar open-collector npn Darlington
outputs, a CMOS data latch for each of the drivers, a 32-bit CMOS
shift register, and CMOS control circuitry. The high-speed CMOS shift
registers and latches allow operation with most microprocessor-based
systems at data input rates above 3.3 MHz. Use of these drivers with
TTL may require input pull-up resistors to ensure an input logic high.
The UCN5833A is supplied in a 40-pin dual in-line plastic package
with 0.600" (15.24 mm) row spacing. At an ambient temperature of
+75°C, all outputs of the DlP-packaged device will sustain 50 mA
continuously. For high-density applications, the UCN5833EP is
available. This 44-lead plastic chip carrier (quad pack) is intended
for surface-mounting on solder lands with 0.050" (1.27 mm) centers.
CMOS serial data outputs permit cascading for applications requiring
additional drive lines.
REGISTER
REGISTER
LATCHES
SUB
OUT
13
19
OUT
14
20
OUT
15
21
22
LOGIC GROUND
23
OUT
17
24
OUT
18
25
OUT
19
26
OUT
20
27
LATCHES
NC
28
NC
18
OUT
16
Dwg. No. A-13,049
FEATURES
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, V
OUT
. . . . . . . . . . .
30 V
Logic Supply Voltage, V
DD
. . . . . . .
7.0 V
Input Voltage Range,
V
IN
. . . . . . . . .
-0.3 V to V
DD
+ 0.3 V
Continuous Output Current,
l
OUT
(each output) . . . . . . . . . .
125 mA
Package Power Dissipation, P
D
(UCN5833A) . . . . . . . . . . . . . . .
3.5 W*
(UCN5833EP) . . . . . . . . . . . . . .
2.5 W*
Operating Temperature Range,
T
A
. . . . . . . . . . . . . .
-20
°
C to +85
°
C
Storage Temperature Range,
T
S
. . . . . . . . . . . . .
-55
°
C to +150
°
C
* Derate linearly to 0 W at +150°C.
I
To 3.3 MHz Data Input Rate
I
30 V Minimum Output Breakdown
I
Darlington Current-Sink Outputs
I
Low-Power CMOS Logic and Latches
Always order by complete part number:
Part Number
UCN5833A
UCN5833EP
Package
40-Pin DIP
44-Lead PLCC
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
UCN5833A
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
SERIAL
DATA IN
POWER
GROUND
STROBE
OUT 1
OUT
OUT
OUT
2
3
1
2
3
4
5
6
7
8
ST
V
DD
CLK
CLOCK
40
LOGIC
SUPPLY
39
SERIAL
DATA OUT
OUTPUT
ENABLE
OUT
32
V
DD
CLOCK
32-BIT SHIFT REGISTER
SERIAL
DATA IN
LATCHES
STROBE
LOGIC
GROUND
SUB
SERIAL DATA
OUT
OE
38
37
36
35
34
33
OUT 31
OUT
30
OUT 29
OUT 28
OUT
27
OUTPUT
ENABLE
4
5
6
7
8
9
MOS
BIPOLAR
REGISTER
REGISTER
OUT
OUT
OUT
OUT
10
11
12
12
LATCHES
LATCHES
OUT
9
32
31
OUT
26
30
29
28
27
26
25
24
OUT
25
OUT
1
OUT
2
OUT
3
POWER OUT
30
OUT
31
OUT
32
GROUND
OUT 24
OUT
23
Dwg. No. A-13,057
OUT 10
14
OUT 11
15
OUT 12
16
OUT 13
17
OUT 14
18
OUT 15
19
OUT 16
20
SUB
OUT 22
OUT 21
OUT 20
OUT 19
TYPICAL INPUT CIRCUIT
V
DD
23
OUT 18
22
OUT 17
IN
21
LOGIC
GROUND
Dwg. No. A-13,048
Dwg. No. A-13,050
SUB
TYPICAL OUTPUT DRIVER
OUT
Dwg. No. A-13,051
115 Northeast Cutoff, Box 15036
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1986, 1995, Allegro MicroSystems, Inc.
5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
DD
= 5 V (unless otherwise noted).
Characteristic
Output Leakage Current
Collector-Emitter
Saturation Voltage
Input Voltage
Symbol
I
CEX
V
CE(SAT)
V
IN(1)
V
IN(0)
Input Current
l
IN(1)
l
IN(0)
Serial Output Voltage
V
OUT(1)
V
OUT(0)
Supply Current
l
DD
V
IN
= 5.0 V
V
IN
= 0 V
I
OUT
= -200
µA
I
OUT
= 200
µA
One output ON, l
OUT
= 100 mA
All outputs OFF
Output Rise Time
Output Fall Time
t
r
t
f
l
OUT
= 100 mA, 10% to 90%
l
OUT
= 100 mA, 90% to 10%
Test Conditions
V
OUT
= 30 V, T
A
= 70°C
l
OUT
= 50 mA
l
OUT
= 100 mA
Min.
—
—
—
3.5
-0.3
—
—
4.5
—
—
—
—
—
Limits
Max.
10
1.2
1.7
5.3
+0.8
1.0
-1.0
—
0.3
1.0
50
500
500
Units
µA
V
V
V
V
µA
µA
V
V
mA
µA
ns
ns
NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I
1
I
2
I
3
... I
N-1
I
N
H
L
X
H
L
R
1
R
2
...
R
1
R
2
...
R
N-2
R
N-1
R
N-2
R
N-1
R
N-1
R
N
X
X
Serial
Data Strobe
Output Input
R
N-1
R
N-1
R
N
X
P
N
L
H
R
1
R
2
R
3
...
P
1
P
2
P
3
...
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
Latch Contents
I
1
I
2
I
3
...
I
N-1
I
N
Output
Enable
Input
Output Contents
I
1
I
2
I
3
... I
N-1
I
N
R
1
R
2
R
3
...
X
X
X
...
R
N-1
R
N
P
N-1
P
N
X
X
H
L
P
1
P
2
P
3
... P
N-1
P
N
H H H ... H
H
P
1
P
2
P
3
...
P
N-1
P
N
X
X
...
P = Present State
R = Previous State
5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
CLOCK
DATA IN
E
STROBE
OUTPUT
ENABLE
G
OUT
N
Dwg. No. A-12,276A
A
B
D
F
C
TIMING CONDITIONS
(V
DD
= 5.0 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ..........................................................................
75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) .............................................................................
75 ns
C.
Minimum Data Pulse Width ................................................................
150 ns
D.
Minimum Clock Pulse Width ...............................................................
150 ns
E.
Minimum Time Between Clock Activation and Strobe .......................
300 ns
F.
Minimum Strobe Pulse Width .............................................................
100 ns
G.
Typical Time Between Strobe Activation and
Output Transition ...........................................................................
500 ns
Serial Data present at the input is transferred to the shift register
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE tied
high) will require that the OUTPUT ENABLE input be low during serial
data entry.
When the OUTPUT ENABLE input is low, all of the output buffers
are disabled (OFF) without affecting the information stored in the
latches or shift register. With the OUTPUT ENABLE input high, the
outputs are controlled by the state of the latches.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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