A5800 and A5801
BiMOS II Latched Drivers
Last Time Buy
These parts are in production but have been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: May 2, 2005
Deadline for receipt of LAST TIME BUY orders: October 28, 2005
Recommended Substitutions:
For new customers or new applications, refer to the
6800
and
6801.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.
5800
AND
5801
UCN5800L
1
14
BiMOS II LATCHED DRIVERS
The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS ICs
merge high-current, high-voltage outputs with CMOS logic. The CMOS
input section consists of 4 or 8 data (‘D’ type) latches with associated com-
mon CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power
outputs are bipolar npn Darlingtons. This merged technology provides
versatile, flexible interface. These BiMOS power interface ICs greatly benefit
the simplification of computer or microprocessor I/O. The UCN5800A and
UCN5800L each contain four latched drivers; the UCN5801A, UCN5801EP,
and UCN5801LW contain eight latched drivers.
The UCN5800A/L and UCN5801A/EP/LW supersede the original
BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These
second-generation devices are capable of much higher data input rates and
will typically operate at better than 5 MHz with a 5 V logic supply. Circuit
operation at 12 V affords substantial improvement over the 5 MHz figure.
The CMOS inputs are compatible with standard CMOS and NMOS
circuits. TTL circuits may mandate the addition of input pull-up resistors.
The bipolar Darlington outputs are suitable for directly driving many periph-
eral/power loads: relays, lamps, solenoids, small dc motors, etc.
All devices have open-collector outputs and integral diodes for
inductive load transient suppression. The output transistors are
capable of sinking 500 mA and will withstand at least 50 V in the OFF state.
Because of limitations on package power dissipation, the simultaneous
operation of all drivers at maximum rated current can only be accomplished
by a reduction in duty cycle. Outputs may be paralleled for higher load
current capability.
The UCN5800A is furnished in a standard 14-pin DIP; the UCN5800L
and UCN5801LW in surface-mountable SOICs; the UCN5801A in a 22-pin
DIP with 0.400" (10.16 mm) row centers; the UCN5801EP in a 28-lead
PLCC.
Data Sheet
26180.10B*
UCN5800A
CLEAR
STROBE
IN
1
IN
2
IN
3
IN
4
GROUND
1
2
3
4
5
6
7
14
V
DD
13
12
OUTPUT
ENABLE
SUPPLY
OUT
1
OUT
2
OUT
3
OUT
4
COMMON
LATCHES
11
10
9
8
Dwg. PP-014A
Note the UCN5800A (DIP) and the UCN5800L
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at
+25
°
C Free-Air Temperature
Output Voltage, V
CE
. . . . . . . . . . . . . . 50 V
Supply Voltage, V
DD
. . . . . . . . . . . . . . 15 V
Input Voltage Range,
V
IN
. . . . . . . . . . . -0.3 V to V
DD
+ 0.3 V
Continuous Collector Current,
l
C
. . . . . . . . . . . . . . . . . . . . . . 500 mA
Package Power Dissipation,
P
D
. . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
T
A
. . . . . . . . . . . . . . . . -20
°
C to +85
°
C
Storage Temperature Range,
T
S
. . . . . . . . . . . . . . . -55
°
C to +150
°
C
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
FEATURES
s
To 4.4 MHz Data Input Rate
s
High-Voltage,
High-Current Outputs
s
Output Transient Protection
s
CMOS, NMOS,
s
Internal Pull-Down Resistors
TTL Compatible Inputs
s
Low-Power CMOS Latches
s
Automotive Capable
Always order by complete part number, e.g.,
UCN5801EP
.
5800
AND
5801
BiMOS II
LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
SUPPLY
V
DD
COMMON
IN
N
OUT
N
STROBE
CLEAR
GROUND
OUTPUT ENABLE
COMMON MOS CONTROL
TYPICAL MOS LATCH
TYPICAL BIPOLAR DRIVE
Dwg. FP-016-1
TYPICAL INPUT CIRCUIT
V
DD
2.5
22-PIN DIP, R
θJA
= 56°C/W
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
28-LEAD PLCC, R
θJA
= 68°C/W
14-PIN DIP, R
θJA
= 73°C/W
2.0
IN
24-LEAD SOIC, R
θJA
= 85°C/W
1.5
1.0
Dwg. EP-010-4A
0.5
14-LEAD SOIC, R
θJA
= 120°C/W
0
25
50
75
100
125
150
AMBIENT TEMPERATURE IN
°
C
Dwg. GP-023-1A
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2002 Allegro MicroSystems, Inc.
5800
AND
5801
BiMOS II
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
DD
= 5 V (unless otherwise noted).
Characteristic
Output Leakage Current
Symbol
I
CEX
Test Conditions
V
CE
= 50 V, T
A
= +25°C
V
CE
= 50 V, T
A
= +70°C
Collector-Emitter
Saturation Voltage
V
CE(SAT)
I
C
= 100 mA
I
C
= 200 mA
I
C
= 350 mA, V
DD
= 7.0 V
Input Voltage
V
IN(0)
V
IN(1)
V
DD
= 12 V
V
DD
= 10 V
V
DD
= 5.0 V (See Note)
Input Resistance
r
IN
V
DD
= 12 V
V
DD
= 10 V
V
DD
= 5.0 V
Supply Current
I
DD(ON)
(Each
Stage)
I
DD(OFF)
(Total)
Clamp Diode
Leakage Current
Clamp Diode Forward Voltage
I
R
V
DD
= 12 V, Outputs Open
V
DD
= 10 V, Outputs Open
V
DD
= 5.0 V, Outputs Open
V
DD
= 12 V, Outputs Open, Inputs = 0 V
V
DD
= 5.0 V, Outputs Open, Inputs = 0 V
V
R
= 50 V, T
A
= +25°C
V
R
= 50 V, T
A
= +70°C
V
F
I
F
= 350 mA
Min.
—
—
—
—
—
—
10.5
8.5
3.5
50
50
50
—
—
—
—
—
—
—
—
Limits
Typ. Max.
—
—
0.9
1.1
1.3
—
—
—
—
200
300
600
1.0
0.9
0.7
—
50
—
—
1.7
50
100
1.1
1.3
1.6
1.0
—
—
—
—
—
—
2.0
1.7
1.0
200
100
50
100
2.0
Units
µA
µA
V
V
V
V
V
V
V
kΩ
kΩ
kΩ
mA
mA
mA
µA
µA
µA
µA
V
NOTE: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic “1”.
STROBE
28
OUTPUT
ENABLE
27
SUPPLY
V
DD
CLEAR
ST
NC
OE
C
NC
NC
26
4
3
2
1
IN
1
IN
2
5
6
7
LATCHES
25
24
23
22
OUT
1
OUT
2
OUT
3
OUT
4
UCN5801EP
(additional pinout diagrams
are on next page)
IN
3
IN
4
IN
5
8
9
21
OUT
5
20
19
OUT
6
OUT
7
IN
6
10
IN
7
11
14
NC
13
NC
17
NC
K
15
16
12
LAMP DIODE
COMMON
GROUND
OUT
8
IN
8
18
Dwg. PP-037
5800
AND
5801
BiMOS II
LATCHED DRIVERS
UCN5801A
CLEAR
STROBE
IN
1
IN
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
GROUND
1
2
3
4
5
6
7
8
9
10
11
LATCHES
CLEAR
F
22
V
DD
21
20
19
18
17
16
15
14
13
12
OUTPUT
ENABLE
SUPPLY
STROBE
A
OUTPUT
ENABLE
C
B
C
B
A
C
B
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
COMMON
G
G
INN
D
OUTN
E
E
Dwg. No. A-10,895A
TIMING CONDITIONS
(Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Strobe Enabled
(Data Set-Up Time) ..........................................................
50 ns
B.
Minimum Data Active Time After Strobe Disabled
(Data Hold Time) ..............................................................
50 ns
C.
Minimum Strobe Pulse Width ..................................................
125 ns
Dwg. PP-015
D.
Typical Time Between Strobe Activation and
Output On to Off Transition ............................................
500 ns
E.
Minimum Time Between Strobe Activation and
Output Off to On Transition ............................................
500 ns
UCN5801LW
CLEAR
STROBE
IN
1
IN
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
GROUND
NO
CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
LATCHES
F.
Minimum Clear Pulse Width ....................................................
300 ns
24
V
DD
23
22
21
20
19
18
17
16
15
14
13
OUTPUT
ENABLE
SUPPLY
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
COMMON
NO
CONNECTION
Dwg. PP-015-1
G.
Minimum Data Pulse Width .....................................................225
ns
Information present at an input is transferred to its latch when the
STROBE is high. A high CLEAR input will set all latches to the output
OFF condition regardless of the data or STROBE input levels. A high
OUTPUT ENABLE will set all outputs to the OFF condition, regardless
of any other input conditions. When the OUTPUT ENABLE is low, the
outputs depend on the state of their respective latches.
TRUTH TABLE
OUTPUT
IN
N
0
1
X
X
X
X
STROBE
1
1
X
X
0
0
CLEAR
0
0
1
X
0
0
ENABLE
0
0
X
1
0
0
t-1
X
X
X
X
ON
OFF
OUT
N
t
OFF
ON
OFF
OFF
ON
OFF
X = irrelevant.
t-1 = previous output state.
t = present output state.
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Worcester, Massachusetts 01615-0036 (508) 853-5000
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