v3.1
40MX and 42MX Automotive FPGA Families
Features
High Capacity
•
•
•
•
•
Single-Chip ASIC Alternative for Automotive
Applications
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
Ease of Integration
•
•
•
•
•
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
Capacity
System Gates
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
Maximum User I/Os
Boundary Scan Test (BST)
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
A40MX02
3,000
–
–
295
–
–
–
147
1
57
–
68
100
80
–
A40MX04
6,000
–
–
547
–
–
–
273
1
69
–
84
100
80
–
A42MX09
14,000
–
348
336
–
–
348
516
2
104
–
84
100, 160
100
176
A42MX16
24,000
–
624
608
–
–
624
928
2
140
–
–
208
100
176
A42MX24
36,000
–
954
912
24
–
954
1,410
2
176
Yes
–
160, 208
–
176
A42MX36
54,000
2,560
1,230
1,184
24
10
1,230
1,822
6
202
Yes
–
208, 240
–
–
Note:
While the automotive-grade MX devices are offered in standard speed grade only, the MX family is also offered in commercial,
industrial and military temperature grades with -F, Std, -1, -2 and -3 speed grades. Refer to the
40MX and 42MX Family FPGAs
datasheet for more details.
May 2006
© 2006 Actel Corporation
i
See the Actel website (www.actel.com) for the latest version of this datasheet.
40MX and 42MX Automotive FPGA Families
Ordering Information
A42MX16 _
PQ
208
A
Application (Temperature Range)
A
= Automotive (–40 to +125˚C)
Package Lead Count
Package Type
PL =
Plastic Leaded Chip Carrier
PQ =
Plastic Quad Flat Pack
TQ =
Thin Quad Flat Pack (1.4 mm)
VQ =
Very Thin Quad Flat Pack (1.0 mm)
Speed Grade
(Blank for Standard)
Part Number
A40MX02
=
3,000 System Gates
A40MX04
=
6,000 System Gates
A42MX09
=
14,000 System Gates
A42MX16
=
24,000 System Gates
A42MX24
=
36,000 System Gates
A42MX36
=
54,000 System Gates
Note:
Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based
on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If
testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to
discuss testing options available.
Plastic Device Resources
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
PLCC
68-Pin
57
–
–
–
–
–
PLCC
84-Pin
–
69
72
–
–
–
PQFP
100-Pin
57
69
83
–
–
–
PQFP
160-Pin
–
–
101
–
125
–
User I/Os
PQFP
208-Pin
–
–
–
140
176
176
PQFP
240-Pin
–
–
–
–
–
202
VQFP
80-Pin
57
69
–
–
–
–
VQFP
100-Pin
–
–
83
83
–
–
TQFP
176-Pin
–
–
104
140
150
–
Note: Package Definitions
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack
Speed Grade and Temperature Grade Matrix
Std
A
✓
Note:
Refer to the
40MX and 42MX Family FPGAs
datasheet for details on
commercial-, industrial- and military-grade MX offerings.
Contact your local Actel representative for device availability.
ii
v3.1
40MX and 42MX Automotive FPGA Families
Table of Contents
40MX and 42MX Automotive FPGA Families
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Timing Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Dual-Port SRAM Timing Waveforms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-25
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Package Pin Assignments
68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
100-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
160-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
80-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
240-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
v3.1
iii
40MX and 42MX Automotive FPGA Families
40MX and 42MX Automotive FPGA Families
General Description
Actels' automotive-grade MX families provide a high-
performance, single-chip solution for shortening the
system design and development cycle, offering a cost-
effective alternative to ASICs for in-cabin telematics and
automobile interconnect applications. The 40MX and
42MX devices are excellent choices for integrating logic
that is currently implemented in multiple PALs, CPLDs,
and FPGAs.
The MX device architecture is based on Actel’s patented
antifuse technology implemented in a 0.45µm triple-
metal CMOS process. With capacities ranging from 3,000
to 54,000 system gates, the MX devices are live on
power-up and have one-fifth the standby power
consumption of comparable FPGAs. Actel’s MX FPGAs
provide up to 202 user I/Os and are available in a wide
variety of packages and speed grades.
The automotive-grade 42MX24 and 42MX36 include
system-level features such as IEEE Standard 1149.1 (JTAG)
Boundary Scan Testing and fast wide-decode modules. In
addition, the A42MX36 device offers dual-port SRAM for
implementing fast FIFOs, LIFOs, and temporary data
storage. The storage elements can efficiently address
applications requiring wide datapath manipulation.
flops can be constructed from logic modules whenever
required in the application.
The 42MX devices contain three types of logic modules:
combinatorial (C-modules), sequential (S-modules) and
decode
(D-modules).
Figure 1-2
illustrates
the
combinatorial logic module. The S-module, shown in
Figure 1-3 on page 1-2,
implements the same
combinatorial logic function as the C-module while
adding a sequential element. The sequential element can
be configured as either a D-flip-flop or a transparent
latch. The S-module register can be bypassed so that it
implements purely combinatorial logic.
A42MX24 and A42MX36 devices contain D-modules,
which are arranged around the periphery of the device.
D-modules contain wide-decode circuitry, providing a
fast, wide-input AND function similar to that found in
CPLD architectures (Figure
1-4 on page 1-2).
The D-
module allows A42MX24 and A42MX36 devices to
perform wide-decode functions at speeds comparable to
CPLDs and PALs. The output of the D-module has a
programmable inverter for active HIGH or LOW
assertion. The D-module output is hardwired to an
output pin, and can also be fed back into the array to be
incorporated into other logic.
MX Architectural Overview
The MX devices are composed of fine-grained building
blocks that enable fast, efficient logic designs. All devices
within these families are composed of logic modules, I/O
modules, routing resources and clock networks, which
are the building blocks for fast logic designs. In addition,
the A42MX36 device contains embedded dual-port
SRAM modules, which are optimized for high-speed
datapath functions such as FIFOs, LIFOs and scratchpad
memory. A42MX24 and A42MX36 also contain wide-
decode modules.
Figure 1-1 •
40MX Logic Module
A0
B0
D00
D01
D10
D11
A1
B1
S1
Y
Logic Modules
The 40MX logic module is an eight-input, one-output
logic circuit designed to implement a wide range of logic
functions with efficient use of interconnect routing
resources (Figure
1-1).
The logic module can implement the four basic logic
functions (NAND, AND, OR and NOR) in gates of two,
three, or four inputs. The logic module can also
implement a variety of D-latches, exclusivity functions,
AND-ORs and OR-ANDs. No dedicated hardwired latches
or flip-flops are required in the array; latches and flip-
v3.1
S0
Figure 1-2 •
42MX C-Module Implementation
1-1
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
