UC1846-SP
www.ti.com...............................................................................................................................................................................................
SLUS871 – JANUARY 2009
RAD-TOLERANT CLASS-V, CURRENT-MODE PWM CONTROLLER
1
FEATURES
QML-V Qualified, SMD 5962-86806
Rad-Tolerant: 30 kRad (Si) TID
(1)
Automatic Feed-Forward Compensation
Programmable Pulse-by-Pulse Current
Limiting
Automatic Symmetry Correction in Push-Pull
Configuration
Enhanced Load Response Characteristics
Parallel-Operation Capability for Modular
Power Systems
Differential Current-Sense Amplifier With Wide
Common-Mode Range
Double-Pulse Suppression
500-mA (Peak) Totem-pole Outputs
±1% Bandgap Reference
Undervoltage Lockout
Soft-Start Capability
Shutdown Terminal
500-kHz Operation
•
•
•
•
•
•
•
•
•
•
•
C/S–
C/S+
NC
E/A+
E/A–
4
5
6
7
8
3 2
V
REF
C/L SS
NC
Shsutdown
V
IN
1 20 19
18
17
16
15
14
9 10 11 12 13
•
•
•
•
FK PACKAGE
(TOP VIEW)
B Out
V
C
NC
Gnd
A Out
(1)
Radiation tolerance is a typical value based upon initial device
qualification with dose rate = 10 mrad/sec. Radiation Lot
Acceptance Testing is available - contact factory for details.
C/L SS
V
REF
C/S–
C/S+
E/A+
E/A–
Comp
C
T
DESCRIPTION
The UC1846 control devices provide all of the necessary features to implement fixed frequency, current mode
control schemes while maintaining a minimum external parts count. The superior performance of this technique
can be measured in improved line regulation, enhanced load response characteristics, and a simpler,
easier-to-design control loop. Topological advantages include inherent pulse-by-pulse current limiting capability,
automatic symmetry correction for push-pull converters, and the ability to parallel “power modules" while
maintaining equal current sharing.
Protection circuitry includes built-in under-voltage lockout and programmable current limit in addition to soft start
capability. A shutdown function is also available which can initiate either a complete shutdown with automatic
restart or latch the supply off.
Other features include fully latched operation, double-pulse suppression, deadline adjust capability, a ±1%
trimmed bandgap reference, and low outputs in the OFF state.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
Comp
C
T
NC
R
T
Sync
J PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Shutdown
V
IN
B Out
V
C
Gnd
A Out
Sync
R
T
UC1846-SP
SLUS871 – JANUARY 2009...............................................................................................................................................................................................
www.ti.com
ORDERING INFORMATION
(1)
T
A
–55°C to 125°C
(1)
(2)
PACKAGE
(2)
CDIP – J
LCCC – FK
ORDERABLE PART NUMBER
5962-8680603VEA
5962-8680603V2A
TOP-SIDE MARKING
UC1846J-SP
UC1846FK-SP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at
www.ti.com.
Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
BLOCK DIAGRAM
VIN 15
5.1 V
REFERENCE
REGULATOR
2
VREF
13 VC
SYNC 10
UVLO
LOCKOUT
F/F
Q
11 A OUT
T
Q
RT
9
OSC
CT
8
C/S-
3
X3
COMP
S R
Q
S
0.5 V
+
Output Stage
C/S+
4
14 B OUT
0.5 mA
E/A+
5
E/A
E/A–
6
12 GND
1
C/L SS
16 SHUTDOWN
COMP
7
350 mV
6k
NOTE: Pin numbers shown are for the J package.
2
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UC1846-SP
Copyright © 2009, Texas Instruments Incorporated
UC1846-SP
www.ti.com...............................................................................................................................................................................................
SLUS871 – JANUARY 2009
ABSOLUTE MAXIMUM RATINGS
(1) (2)
over operating free-air temperature range (unless otherwise noted)
V
CC
I
O
V
I
Supply voltage
Collector supply voltage
Output current, source or sink
Analog input voltage (C/S-, C/S+, E/A+, E/A-, Shutdown)
Reference output current
Sync output current
Error amplifier output current
Soft-start sink current
Oscillator charging current
P
D
T
stg
T
lead
(1)
(2)
Power dissipation
Storage temperature range
Lead temperature (soldering, 10 seconds)
T
A
= 25°C
T
C
= 25°C
40 V
40 V
500 mA
–0.3 V to V
IN
–30 mA
–5 mA
–5 mA
50 mA
5 mA
1000 mW
2000 mW
–65°C to 150°C
300°C
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal.
ELECTRICAL CHARACTERISTICS
V
IN
= 15 V, R
T
= 10kΩ, C
T
= 4.7 nF, T
A
= T
J
= –55°C to 125°C (unless otherwise noted)
PARAMETER
Reference Section
Output voltage
Line regulation
Load regulation
Temperature stability
Total output variation
Output noise voltage
Long-term stability
Short-circuit output current
Oscillator Section
Initial accuracy
Voltage stability
Temperature stability
Sync output high level
Sync output low level
Sync input high level
Sync input low level
Sync input current
Error Amp Section
Input offset voltage
Input bias current
Input offset current
Common mode range
Open-loop voltage gain
Unity-gain bandwidth
CMRR
(1)
V
IN
= 8 V to 40 V
ΔV
O
= 1.2 V to 3 V, V
CM
= 2 V
T
J
= 25°C
(1)
TEST CONDITIONS
T
J
= 25°C, I
O
= 1 mA
V
IN
= 8 V to 40 V
I
L
= 1 mA to 10 mA
Over operating range
Over line, load, and temperature
10 Hz
≤
f
≤
10 kHz, T
J
= 25°C
T
J
= 125°C, 1000 hr
V
REF
= 0 V
T
J
= 25°C
V
IN
= 8 V to 40 V
Over operating range
(1)
(1)
MIN
5.04
TYP
5.10
5
3
0.4
MAX
5.16
20
15
5.2
UNIT
V
mV
mV
mV/°C
V
µV
mV
mA
5
100
5
–10
39
–45
43
–1
–1
3.9
4.35
2.3
47
2
kHz
%
%
V
2.5
2.5
V
V
V
mA
mV
µA
nA
V
dB
MHZ
dB
C
T
= 0 V
C
T
= 0 V
Sync = 5.25 V, C
T
= 0 V
3.9
1.3
0.5
-1
0
80
0.7
75
105
1
100
–0.6
40
250
V
IN
– 2
1.5
5
V
CM
= 0 V to 38 V, V
IN
= 40 V
Parameters ensured by design and/or characterization, if not production tested.
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UC1846-SP
3
Copyright © 2009, Texas Instruments Incorporated
UC1846-SP
SLUS871 – JANUARY 2009...............................................................................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
V
IN
= 15 V, R
T
= 10kΩ, C
T
= 4.7 nF, T
A
= T
J
= –55°C to 125°C (unless otherwise noted)
PARAMETER
PSRR
Output sink current
Output source current
High-level output voltage
Low-level output voltage
Current Sense Amplifier Section
Amplifier gain
Maximum differential input signal
(V
C/S+
– V
C/S–
)
Input offset voltage
CMRR
PSRR
Input bias current
Input offset current
Input common-mode range
Delay to outputs
Current Limit Adjust Section
Current limit offset
Input bias current
Shutdown Terminal Section
Threshold voltage
Input voltage range
Minimum latching current (I
C/S SS
)
(6)
Maximum non-latching current (I
C/S SS
)
Delay to outputs
Output Section
Collector-emitter voltage
Collector leakage current
Output low-level voltage
Output high-level voltage
Rise time
Fall time
Undervoltage Lockout Section
Start-up threshold
Threshold hysteresis
Total Standby Current
Supply current
(2)
(3)
(4)
(5)
(6)
(7)
Parameter measured at trip point of latch with V
E/A+
= V
REF
, V
E/A–
= 0 V.
Amplifier gain defined as: G =
ΔV
Comp
/ΔV
C/S+
; V
C/S+
= 0 to 1 V.
Parameters ensured by design and/or characterization, if not production tested.
Parameter measured at trip point of latch with V
E/A+
= V
REF
, V
E/A–
= 0 V.
Current into C/S SS required to latch circuit in shutdown state.
Current into C/S SS assured not to latch circuit in shutdown state.
17
21
mA
7.7
0.75
8
V
V
V
C
= 40 V
I
SINK
= 20 mA
I
SINK
= 100 mA
I
SOURCE
= 20 mA
I
SOURCE
= 100 mA
C
L
= 1 nF, T
J
= 25°C
C
L
= 1 nF, T
J
= 25°C
(4)
(4)
(7)
TEST CONDITIONS
V
IN
= 8 V to 40 V
V
ID
= -15 mV to -5 V, Comp = 1.2 V
V
ID
= 15 mV to 5 V, Comp = 2.5 V
R
L
= (Comp) 15 kΩ
R
L
= (Comp) 15 kΩ
V
C/S–
= 0 V, C/L SS open
(2) (3)
C/L SS open
(2)
, R
L
(Comp)= 15 kΩ
V
C/L
SS
MIN
80
2
4.3
TYP
105
6
–0.5
4.6
0.7
MAX
UNIT
dB
mA
-0.4
1
3.1
mA
V
V
V/V
V
2.5
1.1
2.75
1.2
5
= 0.5 V, Comp open
(2)
60
60
-10
(2)
25
mV
dB
dB
µA
V
CM
= 1 V to 12 V
V
IN
= 8 V to 40 V
V
C/L
V
C/L
SS
SS
83
84
–2.5
0.08
200
1
V
IN
– 3
500
0.55
= 0.5 V, Comp open
(2)
= 0.5 V, Comp open
µA
V
ns
V
µA
T
J
= 25°C
(4)
V
C/S–
= 0 V, V
C/S+
= 0 V, Comp open
(5)
V
E/A+
= V
REF
, V
E/A–
= 0 V
0.45
-30
250
0
3
T
J
= 25°C
(4)
40
0.5
–10
350
V
IN
1.5
1.5
300
400
mV
V
mA
0.8
600
mA
ns
V
200
0.1
0.4
13
12
13.5
13.5
50
50
300
300
0.4
2.1
µA
V
V
V
V
ns
ns
4
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Product Folder Link(s):
UC1846-SP
Copyright © 2009, Texas Instruments Incorporated
UC1846-SP
www.ti.com...............................................................................................................................................................................................
SLUS871 – JANUARY 2009
APPLICATION INFORMATION
Output deadtime is determined by the external capacitor, C
T
, according to the formula:
τ
d
(
µ
s
)
=
145CT
(
µ
f
)
I
D
= Oscillator discharge current at 25°C is typically 7.5.
For large values of R
T
:
τ
d
(
µ
s
)
≈
145CT
(
µ
f
)
.
Oscillator frequency is approximated by the formula: fT
(
kHz
)
≈
ID
.
3.6
ID -
RT (k
Ω
)
2.2
.
RT
(
k
Ω
)
•
CT
(
µ
f
)
Figure 1. Oscillator Circuit
Figure 2. Error Amplifier Output Configuration
Figure 3. Error Amplifier Gain and Phase vs Frequency
Copyright © 2009, Texas Instruments Incorporated
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Product Folder Link(s):
UC1846-SP
5
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