LVPECL Dual-Frequency
Programmable VCXO
General Description
The IDT8N3DV85 is a LVPECL Dual-Frequency Programmable
VCXO with very flexible frequency and pull-range programming
capabilities. The device uses IDT’s fourth generation FemtoClock
®
NG technology for an optimum of high clock frequency and low
phase noise performance. The device accepts 2.5V or 3.3V supply
and is packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm
x 7mm x 1.55mm package.
The device can be factory-programmed to any two frequencies in the
range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz
to the very high degree of frequency precision of 218Hz or better.
The output frequency is selected by the FSEL pin. The extended
temperature range supports wireless infrastructure, telecommuni-
cation and networking end equipment requirements.
IDT8N3DV85
DATASHEET
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Fourth Generation FemtoClock
®
NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Two factory-programmed output frequencies
VCO frequency programming resolution is 218Hz and better
Factory-programmable VCXO pull range and control voltage
polarity
VCXO pull range programmable from typical ±12.5 to ±787.5ppm
One 2.5V or 3.3V LVPECL clock output
FSEL control input for frequency selection, LVCMOS/LVTTL
compatible
RMS phase jitter @ 622.08MHz (12kHz - 20MHz):0.46ps (typical)
RMS phase jitter @ 622.08MHz (50kHz - 80MHz): 0.47ps (typical)
2.5V or 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm
package
Block Diagram
OSC
114.285 MHz
2
Pin Assignment
÷P
PFD
&
LPF
FemtoClock
®
NG
VCO
1950-2600MHz
VC
1
2
3
6
5
4
V
CC
nQ
Q
÷N
Q
nQ
FSEL
V
EE
÷MINT,
MFRAC
9
VC
Pulldown
A/D
23
Configuration Register (ROM)
(Frequency, Pull range, Polarity)
7
IDT8N3DV85
6-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
FSEL
IDT8N3DV85CCD REVISION A OCTOBER 30, 2013
1
©2013 Integrated Device Technology, Inc.
IDT8N3DV85 Data Sheet
LVPECL DUAL-FREQUENCY PROGRAMMABLE VCXO
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4, 5
6
Name
VC
FSEL
V
EE
Q, nQ
V
CC
Input
Input
Power
Output
Power
Pulldown
Type
Description
VCXO Control Voltage input.
Frequency select pin. See Table 3A for function. LVCMOS/LVTTL
interface levels.
Negative power supply.
Differential clock output. LVPECL interface levels.
Positive power supply.
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
FSEL
VC
Test Conditions
Minimum
Typical
5.5
10
50
Maximum
Units
pF
pF
k
Input Pulldown Resistor
IDT8N3DV85CCD REVISION A OCTOBER 30, 2013
2
©2013 Integrated Device Technology, Inc.
IDT8N3DV85 Data Sheet
LVPECL DUAL-FREQUENCY PROGRAMMABLE VCXO
Function Tables
Table 3A. Frequency Selection
Input
FSEL
0 (default)
1
Operation
Frequency 0
Frequency 1
NOTE: Frequency 0 and 1 are factory-programmed by IDT. Any frequency combination within the available frequency range can be ordered.
For order information, see
FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information
document. .
Table 3B. Output Frequency Range
15.476MHz to 866.67MHz
975MHz to 1,300MHz
NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of
218Hz or better.
IDT8N3DV85CCD REVISION A OCTOBER 30, 2013
3
©2013 Integrated Device Technology, Inc.
IDT8N3DV85 Data Sheet
LVPECL DUAL-FREQUENCY PROGRAMMABLE VCXO
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock f
XTAL
of 114.285MHz.
The PLL includes the FemtoClock
®
VCO along with the Pre-divider
(P), the feedback divider (M) and the post divider (N). The
P, M,
and
N
dividers determine the output frequency based on the f
XTAL
reference. The feedback divider is fractional supporting a huge
number of output frequencies. Internal registers are used to hold up
to two different factory pre-set configuration settings. The
configuration is selected via the FSEL pin. Changing the FSEL
control results in an immediate change of the output frequency to the
selected register values. The
P, M,
and
N
frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator. The output frequency
is determined by the 2-bit pre-divider (P), the feedback divider (M)
and the 7-bit post divider (N). The feedback divider (M) consists of
both a 7-bit integer portion (MINT) and an 18-bit fractional portion
(MFRAC) and provides the means for high-resolution frequency
generation. The output frequency f
OUT
is calculated by:
1
MFRAC
+ 0.5
-
f OUT
=
f XTAL
------------
MINT
+
------------------------------------
P
N
18
2
Frequency Configuration
An order code is assigned to each frequency configuration and the
VCXO pull-range programmed by the factory (default frequencies).
For more information on the available default frequencies and order
codes, please see the Ordering Information Section in this document.
For available order codes, see the
FemtoClock NG
Ceramic-Package XO and VCXO Ordering Product Information
document.
For more information on programming capabilities of the device for
custom frequency and pull-range configurations, see the
FemtoClock
NG Ceramic 5x7 Module Programming Guide.
(1)
Table 3A. Frequency Selection
Input
FSEL
0 (default)
1
Selects
Frequency 0
Frequency 1
IDT8N3DV85CCD REVISION A OCTOBER 30, 2013
4
©2013 Integrated Device Technology, Inc.
IDT8N3DV85 Data Sheet
LVPECL DUAL-FREQUENCY PROGRAMMABLE VCXO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.71V
-0.5V to V
CC
+ 0.5V
50mA
100mA
49.4C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
=
3.3V ± 5%, V
EE
=
0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
130
Maximum
3.465
160
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
=
2.5V ± 5%, V
EE
=
0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
120
Maximum
2.625
155
Units
V
mA
Table 4C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
=
0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
Table 4D. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
=
0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.4
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.5
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
IDT8N3DV85CCD REVISION A OCTOBER 30, 2013
5
©2013 Integrated Device Technology, Inc.
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
