18Mb Pipelined
DDR™II SRAM
Burst of 2
Features
x
x
x
x
x
x
x
x
x
Advance
Information
IDT71P71204
IDT71P71104
IDT71P71804
IDT71P71604
Description
The IDT DDRII
TM
Burst of two SRAMs are high-speed synchronous
memories with a double-data-rate (DDR), bidirectional data port. This
scheme allows maximization of the bandwidth on the data bus by pass-
ing two data items per clock cycle. The address bus operates at single
data rate speeds, allowing the user to fan out addresses and ease
system design while maintaining maximum performance on data trans-
fers.
The DDRII has scalable output impedance on its data output bus and
echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a V
DDQ
and a separate Vref,
allowing the user to designate the interface operational voltage, indepen-
dent of the device core voltage of 1.8V V
DD.
The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
x
x
x
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
Common Read and Write Data Port
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
Multiplexed Address Bus
-
One Read or One Write request per clock cycle
DDR (Double Data Rate) Data Bus
- Two word bursts data per clock
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
-
Output Impedance adjustable from 35 ohms to 70
ohms
1.8V Core Voltage (V
DD
)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Clocking
The DDRII SRAM has two sets of input clocks, namely the K,
K
clocks
and the C,
C
clocks. In addition, the DDRII has an output “echo” clock,
CQ,
CQ.
The K and
K
clocks are the primary device input clocks. The K clock
is used to clock in the control signals (LD, R/W and
BWx
or
NWx),
the
address, and the first word of the data burst during a write operation.
Functional Block Diagram
DATA
REG
(Note 1)
WRITE DRIVER
LD
R
/W
BW
x
(Note3)
CTRL
LOGIC
18M
MEMORY
ARRAY
(Note1)
(Note4)
OUTPUT SELECT
SENSE AMPS
OUTPUT REG
SA
SA
0
ADD
REG
(Note2)
WRITE/READ DECODE
(Note2)
(Note1)
DQ
K
K
C
CLK
GEN
SELECT OUTPUT CONTROL
6112 drw 16
CQ
CQ
C
Notes
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the
BW
is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
MAY 2004
1
©2003 Integrated Device Technology, Inc.
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
DSC-6112/00
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
The
K
clock is used to clock in the control signals (BWx or
NWx),
and the
second word of the data burst during a write operation. The K and
K
clocks are also used internally by the SRAM. In the event that the user
disables the C and
C
clocks, the K and
K
clocks will also be used to clock
the data out of the output register and generate the echo clocks.
The C and
C
clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C
must be presented to the SRAM within the timing tolerances. The
output data from the DDRII will be closely aligned to the C and
C
input,
through the use of an internal DLL. When C is presented to the DDRII
SRAM, the DLL will have already internally clocked the first data word to
arrive at the device output simultaneously with the arrival of the C clock.
The
C
and second data word of the burst will also correspond.
signals can be used to prevent writing any byte or individual nibbles,
or combined to prevent writing one word of the burst. The x18 and
x36 DDRll devices have the ability to address to the individual word
level using the SA0 address, but the burst will continue in a linear
sequence and wrap back on itself. The address will not increment to
the next higher burst address location, but instead will return to it’s
own lower words within the burst location. Similarly when reading x18
and x36 DDRll devices, the read burst will begin at the designated
address, but if the burst is started at any other position than the first
word of the burst, the burst will wrap back on itself and read the first
locations before completing.
Output Enables
The DDRII SRAM automatically enables and disables the DQ[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the DQ outputs will come up in a high impedance
state.
Single Clock Mode
The DDRII SRAM may be operated with a single clock pair. C and
C
may be disabled by tying both signals high, forcing the outputs and echo
clocks to be controlled instead by the K and
K
clocks.
DLL Operation
The DLL in the output structure of the DDRII SRAM can be used to
closely align the incoming clocks C and
C
with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding
Doff
low. With the DLL off, the C and
C
(or K and
K
if C and
C
are not used) will directly clock the output register of the SRAM.
With the DLL off, there will be a propagation delay from the time the clock
enters the device until the data appears at the output.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with V
DDQ
= 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to V
DDQ
.
Echo Clock
The echo clocks, CQ and
CQ,
are generated by the C and
C
clocks
(or K,
K
if C,
C
are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of
CQ.
The rising edge of
C
generates
the rising edge of
CQ
and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing that
the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
Read operations are initiated by holding Read/Write control input
(R/W) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C and
C
clocks.
Write operations are initiated by holding the Read/Write control input
(R/W) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the two
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write or nibble write (BW or
NW)
inputs. On the follow-
ing rising edge of
K,
the second half of the data write burst will be
accepted at the device input with the designated (BW or
NW)
inputs.
DDRII devices internally store two words of the burst as a single,
wide word and will retain their order in the burst. The x8 and x9
DDRII devices do not have the ability to address to the single word
level or reverse the burst order; however the byte and nibble write
6.42
2
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
Description
Data I/O s ignals. Data inputs are sampled on the rising edge of K and
K
during valid write operations. Data
outputs are driven during a valid read operation. The outputs are aligned with the rising edge of both C and
C
during normal operation. When operating in a single clo ck mode (C and
C
tied high), the outputs are aligned
with the rising edge of both K and
K
. When a Read operation is not initiated or
LD
is high (deselected) during
the rising edge of K, DQ[X:O] are automatically driven to high impedance after any previous read operation in
progress completes.
2M x 8 -- DQ[7:0]
2M x 9 -- DQ[8:0]
1M x 18 -- DQ[17:0]
512K x 36 -- DQ[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising
edge of
K
clocks d uring write operations. Used to select which byte is writte n into the device during the
current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on
the same edge as the d ata. Deselecting a Byte Write Select will cause the corre sponding b yte of data to be
ignored and not written in to the device.
2M x 9 --
BW
0
controls DQ[8:0]
1M x 18 --
BW
0
controls DQ[8:0] and
BW
1
controls DQ[17:9]
512K x 36 --
BW
0
controls DQ[8:0],
BW
1
controls DQ[17:9],
BW
2
controls DQ[26:18] and
BW
3
controls DQ[35:27]
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects.
Sampled on the rising edge of the K and
K
clocks during write operations. Used to select which nibble is
written into the device during the current portion of the write operations. Nibbles not written remain unaltered.
All the nibble writes are s ampled on the same edge as the data. Dese lecting a Nibble Write Select will cause
the corresponding nibble of data to be ignored and not written in to the device.
DQ[X:0]
Input/Output
Synchronous
BW
0
,
BW
1,
BW
2
,
BW
3
Input
Synchronous
NW
0,
NW
1
Input
Synchronous
SA
Input
Synchronous
Input
Synchronous
Input
Synchronous
Address Inputs. Address es are sampled on the rising edge of K cloc k during active read or write operations.
Burst count address bit on x18 and x36 DDRll devices. This bit allows reversing the burs t order in read or
write operations, or addressing to the individual word of a burst.
Load Control Logic: Sampled on the rising edge of K. If
LD
is low, a two word burst read or write operation
will initiate as designated by the R/
W
inp ut. If
LD
is high during the rising edge of K, operations in progress
will complete, but new operations will not be initiated.
Read or Write Control Log ic. If
LD
is low during the rising edge of K, the R
/W
indicates whether a new
operation should be a read or write. If R/
W
is high, a read op eration will be initiated, if R/
W
is low, a write
operation will be initiated. If the
LD
input is high during the rising e dge of K, the R/
W
input will be ignored.
Positive Output Clock Input. C is used in conjunction with
C
to clock out the Read data fro m the device. C
and
C
can be used toge ther to deskew the flight times of various devices on the board back to the controller.
See application example for further details.
Negative Output Clock Input.
C
is used in conjunction with C to clock out the Read data from the device. C
and
C
can be used toge ther to deskew the flight times of various devices on the board back to the controller.
See application example for further details.
Positive Input Clock. The rising ed ge of K is used to capture synchronous inputs to the device and to drive
out data through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
Negative Input Clock.
K
is used to capture synchronous inputs being presented to the device and to drive out
data through DQ[X:0] when in single clock mode.
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals are free running and do not stop when
the output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. DQ[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and
ground. Alternately, this pin can be connected directly to V
DDQ
, which enables the minimum impedance mode.
This pin cannot be connec ted directly to GND or left unconnected.
6112 tbl 02a
SA
0
LD
R
/W
Input
Synchronous
C
Input Clock
C
Input Clock
K
Input Clock
K
Input Clock
CQ,
CQ
Output Clock
ZQ
Input
6.42
3
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions continued
Symbol
Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with
the DLL turned off will be different from those listed in this data sheet. There will be an
increased propagation delay from the incidence of C and
C
to DQ, or K and
K
to DQ as
configured. The propagation delay is not a tested parameter, but will be similar to the
propagation delay of other SRAM devices in this speed grade.
TDO pin for JTAG
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to V
DD
when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to V
DD
when the pin is unconnected.
Doff
Input
TDO
TCK
TDI
TMS
NC
Output
Input
Input
Input
No Connect No connects inside the package. Can be tied to any voltage level
Input
Reference
Power
Supply
Ground
Power
Supply
Reference Voltage input. Static input used to set the reference level for HSTL inputs and
outputs as well as AC measurement points.
Power supply inputs to the core of the device. Should be connected to a 1.8V power
supply.
Ground for the device. Should be connected to ground of the system.
Power supply for the outputs of the device. Should be connected to a 1.5V power supply
for HSTL or scaled to the desired output voltage.
6112 tbl 02b
V
REF
V
DD
V
SS
V
DDQ
6.42
4
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration 2M x 8
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
V
SS
/
SA
(2)
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ
6
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ
4
NC
DQ
5
V
DDQ
NC
NC
NC
NC
NC
DQ
7
SA
4
R
/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
6
7
NC
8
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/
SA
(1)
NC
NC
NC
NC
NC
NC
V
REF
DQ
1
NC
NC
NC
NC
NC
TMS
6112 tbl 12
11
CQ
DQ
3
NC
NC
DQ
2
NC
NC
ZQ
NC
NC
DQ
0
NC
NC
NC
TDI
CQ
NC
NC
NC
NC
NC
NC
NW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
NW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
Doff
NC
NC
NC
NC
NC
NC
TDO
C
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
5
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